ISL6323B Datasheet, PDF (19/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323B
Output-Voltage Offset Programming
The ISL6323B allows the designer to accurately adjust the
offset voltage by connecting a resistor, R_OFS, from the OFS
pin to VCC or GND. When R_OFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I_OFS) to flow into the FB pin
and out of the OFS pin. If R_OFS is connected to ground, the
voltage across it is regulated to 0.3V, and I_OFS flows into the
OFS pin and out of the FB pin. The offset current flowing
through the resistor between VDIFF and FB will generate the
desired offset voltage which is equal to the product
(I_OFS x R_FB). These functions are shown in Figures 9 and 10.
Once the desired output offset voltage has been determined,
use the following formulas to set R_OFS:
For Positive Offset (connect R_OFS to GND):
R_OFS
=
-⁰---^.--³-----^×-----^R----^F----^B--
V_OFFSET
(EQ. 14)
For Negative Offset (connect R_OFS to VCC):
R_OFS
=
-¹---^.--⁶-----^×-----^R----^F----^B--
V_OFFSET
(EQ. 15)
VDIFF
-
V_{OFS RFB}
+
VREF
E/A
FB
I_OFS
VCC
R_OFS
OFS
ISL6323B
+
0.3V
-
-
1.6V
+
GND
VCC
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
The AMD processor does not step the output voltage
commands up or down to the target voltage, but instead
passes only the target voltage to the ISL6323B through
either the PVI or SVI interface. The ISL6323B manages the
resulting VID-on-the-Fly transition in a controlled manner,
supervising a safe output voltage transition without
discontinuity or disruption. The ISL6323B begins slewing the
DAC at 3.25mV/μs until the DAC and target voltage are
equal. Thus, the total time required for a dynamic VID
transition is dependent only on the size of the DAC change.
V_OUT
+
V_{OFS RFB}
-
VREF
E/A
FB
I_OFS
R_OFS
OFS
ISL6323B
GND
+
0.3V
-
-
1.6V
+
GND
VCC
FIGURE 10. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
To further improve dynamic VID performance, ISL6323B
also implements a proprietary DAC smoothing feature. The
external series RC components connected between DVC
and FB limit any stair-stepping of the output voltage during a
VID-on-the-Fly transition.
Compensating Dynamic VID Transitions
During a VID transition, the resulting change in voltage on
the FB pin and the COMP pin causes an AC current to flow
through the error amplifier compensation components from
the FB to the COMP pin. This current then flows through the
feedback resistor, R_FB, and can cause the output voltage to
overshoot or undershoot at the end of the VID transition. In
order to ensure the smooth transition of the output voltage
during a VID change, a VID-on-the-fly compensation
network is required. This network is composed of a resistor
and capacitor in series, R_DVC and C_DVC, between the DVC
and the FB pin.
VSEN
R_FB ^IDVC ^{= I}C
I_C
I_DVC
C_DVC
DVC
R_DVC
C_C
FB
R_C
COMP
VDAC+RGND
-
+ _ERROR
AMPLIFIER
ISL6323B INTERNAL CIRCUIT
FIGURE 11. DYNAMIC VID COMPENSATION NETWORK
19
FN6879.0
March 23, 2009