ISL6323B Datasheet, PDF (28/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323B
Inductor DCR Current Sensing Component Fine
Tuning
V_IN
IL_n
UGATE(n)
MOSFET
L
DCR
V_OUT
ΔV₁
DRIVER
LGATE(n)
INDUCTOR
V_L(s)
C_OUT
V_C(s)
R₁
C
ISL6323B INTERNAL CIRCUIT
R₂
ΔV₂
V_OUT
I_TRAN
ΔI
I_n
K_I
KI
=
-⁴----⁰---^k----^Ω----
RSET
SAMPLE
+
-
I_SEN
V_C(s)
R_ISEN
2.4kΩ
ISENn-
ISENn+
RSET
R_SET
VCC
FIGURE 20. DCR SENSING CONFIGURATION
Due to errors in the inductance and/or DCR it may be
necessary to adjust the value of R₁ and R₂ to match the time
constants correctly. The effects of time constant mismatch
can be seen in the form of droop overshoot or undershoot
during the initial load transient spike, as shown in Figure 21.
Follow the steps below to ensure the R-C and inductor
L/DCR time constants are matched accurately.
1. If the regulator is not utilizing droop, modify the circuit by
placing the frequency set resistor between FS and
Ground for the duration of this procedure.
2. Capture a transient event with the oscilloscope set to
about L/DCR/2 (sec/div). For example, with L = 1µH and
DCR = 1mΩ, set the oscilloscope to 500µs/div.
3. Record ΔV1 and ΔV2 as shown in Figure 21.
FIGURE 21. TIME CONSTANT MISMATCH BEHAVIOR
4. Select new values, R_1,NEW and R_2,NEW, for the time
constant resistors based on the original values, R_1,OLD
and R_2,OLD, using Equations 48 and 49.
R1, _NEW = R1, _OLD ⋅ ^ΔΔ----VV----12--
(EQ. 48)
R2, _NEW
=
R2,
OL
D
⋅
Δ_----V_----1--
ΔV2
(EQ. 49)
5. Replace R₁ and R₂ with the new values and check to see
that the error is corrected. Repeat the procedure if
necessary.
Loadline Regulation Resistor
The loadline regulation resistor, labeled R_FB in Figure 8,
sets the desired loadline required for the application.
Equation 50 can be used to calculate R_FB.
R_FB
=
-----------------^V----^D----^R----^O-----^O----^P----^M-----^A----^X------------------
4_----0_---0_{-- â‹} ^I_--^O_-----^U_----^T_---M_-----A_----X_{-- ⋅ -}D_-----C_-----R_{--- ⋅ K}
3
N
R_SET
(EQ. 50)
Where R_ISEN is the 2.4kΩ internal current sense resistor, K_I
is defined in Equation 10 and K is defined in Equation 7.
If no loadline regulation is required, FS resistor should be
tied between the FS pin and VCC. To choose the value for
R_FB in this situation, please refer to “Compensation Without
Loadline Regulation” on page 29.
Compensation With Loadline Regulation
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R_C and C_C.
28
FN6879.0
March 23, 2009