ISL6323B Datasheet, PDF (15/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323B
voltage on the VID1/SEL pin. When the EN pin is toggled
HIGH, the status of the VID1/SEL pin will latch the ISL6323B
into either PVI or SVI mode. This latching occurs on the rising
edge of the EN signal. If the VID1/SEL pin is held LOW during
the latch, the ISL6323B will be placed into SVI mode. If the
VID1/SEL pin is held HIGH during the latch, the ISL6323B will
be placed into PVI mode. For the ISL6323B to properly enter
into either mode, the level on the VID1/SEL pin must be stable
no less that 1µs prior to the EN signal transitioning from low to
high.
6-bit Parallel VID Interface (PVI)
With the ISL6323B in PVI mode, the single-phase North
Bridge regulator is disabled. Only the multi-phase controller
is active in PVI mode to support uniplane VDD only
processors. Table 1 shows the 6-bit parallel VID codes and
the corresponding reference voltage.
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TABLE 1. 6-BIT PARALLEL VID CODES
VID4 VID3 VID2 VID1 VID0 VREF
0
0
0
0
0
1.5500
0
0
0
0
1
1.5250
0
0
0
1
0
1.5000
0
0
0
1
1
1.4750
0
0
1
0
0
1.4500
0
0
1
0
1
1.4250
0
0
1
1
0
1.4000
0
0
1
1
1
1.3750
0
1
0
0
0
1.3500
0
1
0
0
1
1.3250
0
1
0
1
0
1.3000
0
1
0
1
1
1.2750
0
1
1
0
0
1.2500
0
1
1
0
1
1.2250
0
1
1
1
0
1.2000
0
1
1
1
1
1.1750
1
0
0
0
0
1.1500
1
0
0
0
1
1.1250
1
0
0
1
0
1.1000
1
0
0
1
1
1.0750
1
0
1
0
0
1.0500
1
0
1
0
1
1.0250
1
0
1
1
0
1.0000
1
0
1
1
1
0.9750
1
1
0
0
0
0.9500
1
1
0
0
1
0.9250
1
1
0
1
0
0.9000
1
1
0
1
1
0.8750
1
1
1
0
0
0.8500
TABLE 1. 6-BIT PARALLEL VID CODES (Continued)
VID5 VID4 VID3 VID2 VID1 VID0 VREF
0
1
1
1
0
1
0.8250
0
1
1
1
1
0
0.8000
0
1
1
1
1
1
0.7750
1
0
0
0
0
0
0.7625
1
0
0
0
0
1
0.7500
1
0
0
0
1
0
0.7375
1
0
0
0
1
1
0.7250
1
0
0
1
0
0
0.7125
1
0
0
1
0
1
0.7000
1
0
0
1
1
0
0.6875
1
0
0
1
1
1
0.6750
1
0
1
0
0
0
0.6625
1
0
1
0
0
1
0.6500
1
0
1
0
1
0
0.6375
1
0
1
0
1
1
0.6250
1
0
1
1
0
0
0.6125
1
0
1
1
0
1
0.6000
1
0
1
1
1
0
0.5875
1
0
1
1
1
1
0.5750
1
1
0
0
0
0
0.5625
1
1
0
0
0
1
0.5500
1
1
0
0
1
0
0.5375
1
1
0
0
1
1
0.5250
1
1
0
1
0
0
0.5125
1
1
0
1
0
1
0.5000
1
1
0
1
1
0
0.4875
1
1
0
1
1
1
0.4750
1
1
1
0
0
0
0.4625
1
1
1
0
0
1
0.4500
1
1
1
0
1
0
0.4375
1
1
1
0
1
1
0.4250
1
1
1
1
0
0
0.4125
1
1
1
1
0
1
0.4000
1
1
1
1
1
0
0.3875
1
1
1
1
1
1
0.3750
Serial VID Interface (SVI)
The on-board Serial VID interface (SVI) circuitry allows the
processor to directly drive the core voltage and Northbridge
voltage reference level within the ISL6323B. The SVC and
SVD states are decoded with direction from the PWROK and
VFIXEN inputs as described in the following sections. The
ISL6323B uses a digital to analog converter (DAC) to
generate a reference voltage based on the decoded SVI
value. See Figure 7 for a simple SVI interface timing
diagram.
15
FN6879.0
March 23, 2009