ISL6323B Datasheet, PDF (25/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323B
A third component involves the lower MOSFET
reverse-recovery charge, Q_rr. Since the inductor current has
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q_rr, it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P_UP,3.
P_UP,3 = V_IN ⋅ Q_rr ⋅ f_S
(EQ. 25)
Finally, the resistive part of the upper MOSFET is given in
Equation 26 as P_UP,4.
P_UP,4 ≈ r_DS(ON) ⋅
⎛
⎜
⎝
I--_{M---⎟⎞}
N⎠
2
⋅
d
+
I--_P-------P--²
12
(EQ. 26)
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 23, 24, 25 and 26. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 4V and its capacitance value can be
chosen from Equation 27:
C_{BOOT_CAP} ≥ _Δ-----_V----_B-^Q---_O--^G--_O--^A---_T-^T--_{_}-^E--_C----_A----_P-
Q_GATE=
Q_{-----G-----1----}•_-----P_----V_-----C_----C_---
V_GS1
•
N_Q1
(EQ. 27)
where Q_G1 is the amount of gate charge per upper MOSFET
at V_GS1 gate-source voltage and N_Q1 is the number of
control MOSFETs. The ΔV_{BOOT_CAP} term is defined as the
allowable droop in the rail of the upper gate drive.
Gate Drive Voltage Versatility
The ISL6323B provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2 _20nC
Q_GATE = 100nC
50nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV_{BOOT_CAP} (V)
FIGURE 17. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W
at room temperature. See “Layout Considerations” on
page 32 for thermal transfer improvement suggestions.
When designing the ISL6323B into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P_{Qg_TOT}, due to the gate charge of MOSFETs and the
integrated driver’s internal circuitry and their corresponding
average driver current can be estimated with Equations 28
and 29, respectively.
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q ⋅ VCC
P _{Q g _Q1}
=
3_--
2
⋅
Q_G1
⋅
P
V
CC
⋅
F_S
W
⋅
N_Q
1
⋅
N_P
H
ASE
(EQ. 28)
P_{Qg_Q2} = Q_G2 ⋅ PVCC ⋅ F_SW ⋅ N_Q2 ⋅ N_PHASE
(EQ. 29)
I_DR
=
⎛
⎝
3_--
2
⋅
Q_G1
⋅
N
Q1
+
Q_G2
⋅
N_Q
⎞
2⎠
⋅ N_PHASE ⋅ F_SW + I_Q
25
FN6879.0
March 23, 2009