ISL6323B Datasheet, PDF (20/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323B
This VID-on-the-fly compensation network works by
sourcing AC current into the FB node to offset the effects of
the AC current flowing from the FB to the COMP pin during a
VID transition. To create this compensation current the
ISL6323B sets the voltage on the DVC pin to be 2x the
voltage on the REF pin. Since the error amplifier forces the
voltage on the FB pin and the REF pin to be equal, the
resulting voltage across the series RC between DVC and FB
is equal to the REF pin voltage. The RC compensation
components, R_DVC and C_DVC, can then be selected to
create the desired amount of compensation current.
The amount of compensation current required is dependant
on the modulator gain of the system, K1, and the error
amplifier R-C components, R_C and C_C, that are in series
between the FB and COMP pins. Use Equations 17, 18 and
19 to calculate the RC component values, R_DVC and C_DVC,
for the VID-on-the-fly compensation network. For these
equations: V_IN is the input voltage for the power train; V_P-P
is the oscillator ramp amplitude (1.5V); and R_C and C_C are
the error amplifier R-C components between the FB and
COMP pins.
K1
=
--^V----^I--^N----
V_P-P
A
=
-----^K-----¹------
K1 – 1
(EQ. 16)
R_RCOMP = A × R_C
(EQ. 17)
C_RCOMP
=
C_-----C--
A
(EQ. 18)
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high
efficiency from the reduced freewheeling time of the lower
MOSFET body-diode conduction, and to prevent the upper and
lower MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V (forward/reverse
inductor current). At this time the UGATE is released to rise. An
auto-zero comparator is used to correct the r_DS(ON) drop in the
phase voltage preventing false detection of the -0.3V phase
level during r_DS(ON) conduction period. In the case of zero
current, the UGATE is released after 35ns delay of the LGATE
dropping below 0.5V. When LGATE first begins to transition
low, this quick transition can disturb the PHASE node and
cause a false trip, so there is 20ns of blanking time once
LGATE falls until PHASE is monitored.
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn-on.
Initialization
Prior to initialization, proper conditions must exist on the EN,
VCC, PVCC1_2, PVCC_NB, ISEN3-, and ISEN4- pins. When
the conditions are met, the controller begins soft-start. Once
the output voltage is within the proper window of operation,
the controller asserts PGOOD.
ISL6323B INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
PVCC1_2
POR
CIRCUIT
PVCC_NB
+12V
ENABLE
COMPARATOR
+
-
10.7kΩ
EN
1.00kΩ
0.86V
SOFT-START
AND
FAULT LOGIC
CHANNEL
DETECT
ISEN3-
ISEN4-
FIGURE 12. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
Power-On Reset
The ISL6323B requires VCC, PVCC1_2, and PVCC_NB
inputs to exceed their rising POR thresholds before the
ISL6323B has sufficient bias to guarantee proper operation.
The bias voltage applied to VCC must reach the internal
power-on reset (POR) rising threshold. Once this threshold
is reached, the ISL6323B has enough bias to begin checking
the driver POR inputs, EN, and channel detect portions of
the initialization cycle. Hysteresis between the rising and
falling thresholds assure the ISL6323B will not advertently
turn off unless the bias voltage drops substantially (see
Electrical Specifications on page 6).
The bias voltage applied to the PVCC1_2 and PVCC_NB
pins power the internal MOSFET drivers of each output
channel. In order for the ISL6323B to begin operation, both
PVCC inputs must exceed their POR rising threshold to
guarantee proper operation of the internal drivers.
Hysteresis between the rising and falling thresholds assure
that once enabled, the ISL6323B will not inadvertently turn
off unless the PVCC bias voltage drops substantially (see
Electrical Specifications on page 6). Depending on the
number of active CORE channels determined by the Phase
20
FN6879.0
March 23, 2009