ISL6323B Datasheet, PDF (18/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323B
POWER SAVINGS MODE: PSI_L
Bit 7 of the Serial VID codes transmitted as part of the 8-bit
data phase over the SVI bus is allocated for the PSI_L. If
Bit 7 is 0, then the processor is at an optimal load for the
regulator to enter power savings mode. If Bit 7 is 1, then the
regulator should not be in power savings mode.
With the ISL6323B, Power Savings mode is realized through
phase shedding. Once a Serial VID command with Bit 7 set to 0
is received, the ISL6323B will shed all phases in a sequential
manner until only Channel 1 and Channel 2 are switching. If
active, Channel 4 will be shed first, followed by Channel 3.
When a phase is shed, that phase will not go into a tri-state
mode until that phase would have had its PWM go HIGH.
When leaving Power Savings Mode, through the reception of
a Serial VID command with Bit 7 set to 1, the ISL6323B will
sequentially turn on phases starting with Phase 3. When a
phase is being reactivated, it will not leave a tri-state until the
PWM of that phase goes HIGH.
If, while in Power Savings Mode, a Serial VID command is
received that forces a VID level change while maintaining
Bit 7 at 0, the ISL6323B will first exit the Power Savings
Mode state as described above. The output voltage will then
be stepped up or down to the appropriate VID level. Finally,
the ISL6323B will then re-enter Power Savings Mode.
Voltage Regulation
The integrating compensation network shown in Figure 8
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage and offset
errors in the OFS current source, remote-sense and error
amplifiers. Intersil specifies the guaranteed tolerance of the
ISL6323B to include the combined tolerances of each of
these elements.
The output of the error amplifier, V_COMP, is used by the
modulator to generate the PWM signals. The PWM signals
control the timing of the Internal MOSFET drivers and
regulate the converter output so that the voltage at FB is equal
to the voltage at REF. This will regulate the output voltage to
be equal to Equation 11. The internal and external circuitry
that controls voltage regulation is illustrated in Figure 8.
V_OUT = V_REF – V_OFS – V_DROOP
(EQ. 11)
The ISL6323B incorporates differential remote-sense
amplification in the feedback path. The differential sensing
removes the voltage error encountered when measuring the
output voltage relative to the controller ground reference point
resulting in a more accurate means of sensing output voltage.
Load-Line (Droop) Regulation
By adding a well controlled output impedance, the output
voltage can effectively be level shifted in a direction which
works to achieve a cost-effective solution can help to reduce
the output-voltage spike that results from fast load-current
demand changes.
EXTERNAL CIRCUIT
FS
R_FS
COMP
ISL6323B INTERNAL CIRCUIT
DROOP
CONTROL
TO
OSCILLATOR
C_C
R_C
FB
R_FB
+
(V_DROOP + V_OFS)
-
+
V_OUT
-
VSEN
RGND
8 I_AVG
I_OFS
-
V_COMP
+ _ERROR
AMPLIFIER
2k
∑
VID
DAC
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, with the FS resistor tied to ground, a
current 8x the average current of all active channels, 8*I_AVG,
flows from FB through a load-line regulation resistor R_FB.
The resulting voltage drop across R_FB is proportional to the
output current, effectively creating an output voltage droop
with a steady-state value defined as Equation 12:
V_DROOP = I_AVG ⋅ R_FB
(EQ. 12)
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage as a function of load current is
shown in Equation 13.
V_OUT
=
V_REF
–
V_O
F
S
–
⎛
⎜
⎝
-^I-^O-----^U----^T--
N
⋅
D
C
R
⋅
⎛
⎝
4_----0_---0_--
3
⋅
R^-----_S^--1--_E^----_T^{- ⎠⎞}
⋅K⋅
⎞
R _{F B⎠⎟}
(EQ. 13)
In Equation 13, V_REF is the reference voltage, V_OFS is the
programmed offset voltage, I_OUT is the total output current
of the converter, K_I is an internal gain determined by the
R_SET resistor connected to the RSET pin (K_I is defined in
Equation 10), K is the DC gain of the RC filter across the
inductor (K is defined in Equation 7), N is the number of
active channels, and DCR is the Inductor DCR value.
18
FN6879.0
March 23, 2009