ISL6323B Datasheet, PDF (13/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323B
EXTERNAL CIRCUIT
APA
C_APA
R_{APA VAPA,TRIP}
COMP
ISL6323B INTERNAL CIRCUIT
100µA
LOW
PASS
FILTER
+
APA
-
TO APA
CIRCUITRY
ERROR
AMPLIFIER
FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION
The APA trip level is the amount of DC offset between the
COMP pin and the APA pin. This is the voltage excursion
that the APA and COMP pins must have during a transient
event to activate the Adaptive Phase Alignment circuitry.
This APA trip level is set through a resistor, R_APA, that
connects from the APA pin to the COMP pin. A 100µA
current flows across R_APA into the APA pin to set the APA
trip level as described in Equation 4. An APA trip level of
500mV is recommended for most applications. A 0.1µF
capacitor, C_APA, should also be placed across the R_APA
resistor to help with noise immunity.
V_{APA, TRIP} = R_APA ⋅ 100 × 10^–6
(EQ. 4)
PWM Operation
The timing of each core channel is set by the number of
active channels. Channel detection on the ISEN3- and
ISEN4- pins selects 2-Channel to 4-Channel operation for
the ISL6323B. The switching cycle is defined as the time
between PWM pulse termination signals of each channel.
The cycle time of the pulse signal is the inverse of the
switching frequency set by the resistor between the FS pin
and ground. The PWM signals command the MOSFET
driver to turn on/off the channel MOSFETs.
For 4-channel operation, the channel firing order is 1-2-3-4:
PWM3 pulse happens 1/4 of a cycle after PWM4, PWM2
output follows another 1/4 of a cycle after PWM3, and
PWM1 delays another 1/4 of a cycle after PWM2. For
3-channel operation, the channel firing order is 1-2-3.
Connecting ISEN4- to VCC selects three channel operation
and the pulse times are spaced in 1/3 cycle increments. If
ISEN3- is connected to VCC, two channel operation is selected
and the PWM2 pulse happens 1/2 of a cycle after PWM1 pulse.
Continuous Current Sampling
In order to realize proper current-balance, the currents in
each channel are sampled continuously every switching
cycle. During this time, the current-sense amplifier uses the
ISEN inputs to reproduce a signal proportional to the
inductor current, I_L. This sensed current, I_SEN, is simply a
scaled version of the inductor current.
13
PWM
SWITCHING PERIOD
I_L
I_SEN
TIME
FIGURE 4. CONTINUOUS CURRENT SAMPLING
The ISL6323B supports Inductor DCR current sensing to
continuously sample each channel’s current for channel-current
balance. The internal circuitry, shown in Figure 4 represents
Channel N of an N-Channel converter. This circuitry is repeated
for each channel in the converter, but may not be active
depending on how many channels are operating.
Inductor windings have a characteristic distributed
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 5. The channel current
I_Ln, flowing through the inductor, passes through the DCR.
Equation 5 shows the S-domain equivalent voltage, V_L,
across the inductor.
V_L(s) = I_Ln ⋅ (s ⋅ L + DCR)
(EQ. 5)
A simple R-C network across the inductor (R₁, R₂ and C)
extracts the DCR voltage, as shown in Figure 5. The voltage
across the sense capacitor, V_C, can be shown to be
proportional to the channel current I_Ln, shown in Equation 6.
⎛
⎝
--^s-----^â‹---^L---
DCR
+
1_⎠⎞
V_C(s)
=
-------------------------------------------------------
⎛
⎜
⎝
s
⋅
(_---R_-----1----⋅_---R_----2----)
R₁ + R₂
⋅
C
+
⎞
1⎟
⎠
⋅
K
⋅
D
C
R
⋅
I_Ln
(EQ. 6)
Where:
K
=
-------^R-----²--------
R₂ + R₁
(EQ. 7)
If the R-C network components are selected such that the
RC time constant matches the inductor L/DCR time constant
(see Equations 7 and 8), then V_C is equal to the voltage drop
across the DCR multiplied by the ratio of the resistor divider,
K. If a resistor divider is not being used, the value for K is 1..
------^L-------
DCR
=
-^R-----¹----^â‹---^R-----²--
R₁ + R₂
⋅
C
(EQ. 8)
FN6879.0
March 23, 2009