ISL6328 Datasheet, PDF (29/33 Pages) Intersil Corporation – Dual PWM Controller For Powering AMD SVI Split-Plane Processors

0.3 _{IL(P-P) = 0}
I_L(P-P) = 0.25 I_O
0.2
I_L(P-P) = 0.5 I_O
I_L(P-P) = 0.75 I_O
ISL6328
0.3
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_O/V_IN)
FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR 4-PHASE CONVERTER
For a four-phase design, use Figure 23 to determine the
input-capacitor RMS current requirement set by the duty cycle,
maximum sustained output current (I_O), and the ratio of the
peak-to-peak inductor current (I_L(P-P)) to I_O. Select a bulk
capacitor with a ripple current rating which will minimize the
total number of input capacitors required to support the RMS
current calculated.
The voltage rating of the capacitors should also be at least 1.25x
greater than the maximum input voltage. Figures 24 and 25 provide
the same input RMS current information for three-phase and
2-phase designs respectively. Use the same approach for selecting
the bulk capacitor type and number.
0.3
I_L(P-P) = 0
I_L(P-P) = 0.25 I_O
I_L(P-P) = 0.5 I_O
I_L(P-P) = 0.75 I_O
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_IN/V_O)
FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS CURRENT
FOR 3-PHASE CONVERTER
Low capacitance, high-frequency ceramic capacitors are needed in
addition to the input bulk capacitors to suppress leading and
falling edge voltage spikes. The spikes result from the high current
slew rate produced by the upper MOSFET turn on and off. Select
low ESL ceramic capacitors and place one as close as possible to
each upper MOSFET drain to minimize board parasitics and
maximize suppression.
0.1
I_L(P-P) = 0
I_L(P-P) = 0.5 I_O
I_L(P-P) = 0.75 I_O
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_IN/V_O)
FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with which
the current transitions from one device to another causes voltage
spikes across the interconnecting impedances and parasitic
circuit elements. These voltage spikes can degrade efficiency,
radiate noise into the circuit and lead to device overvoltage
stress. Careful component selection, layout, and placement
minimizes these voltage spikes. Consider, as an example, the
turnoff transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET was carrying channel current. During the turnoff,
current stops flowing in the upper MOSFET and is picked up by
the lower MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes.
There are two sets of critical components in a DC/DC converter
using a ISL6328 controller. The power components are the most
critical because they switch large amounts of energy. Next are
small signal components that connect to sensitive nodes or
supply critical bypassing current and signal coupling.
The power components should be placed first, which include the
MOSFETs, input and output capacitors, and the inductors. It is
important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each.
Symmetrical layout allows heat to be dissipated equally across all
power trains. Equidistant placement of the controller to the CORE
and NB power trains it controls through the integrated drivers
helps keep the gate drive traces equally short, resulting in equal
trace impedances and similar drive capability of all sets of
MOSFETs.
When placing the MOSFETs try to keep the source of the upper
FETs and the drain of the lower FETs as close as thermally possible.
Input high-frequency capacitors, C_HF, should be placed close to the
drain of the upper FETs and the source of the lower FETs. Input
bulk capacitors, CBULK, case size typically limits following the
same rule as the high-frequency input capacitors. Place the input
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FN7621.1
June 7, 2011