ISL6328 Datasheet, PDF (25/33 Pages) Intersil Corporation – Dual PWM Controller For Powering AMD SVI Split-Plane Processors

ISL6328
In Equations 30 and 31, P_{Qg_Q1} is the total upper gate drive
power loss and P_{Qg_Q2} is the total lower gate drive power loss;
the gate charge (Q_G1 and Q_G2) is defined at the particular gate to
source drive voltage PVCC in the corresponding MOSFET data
sheet; I_Q is the driver total quiescent current with no load at both
drive outputs; N_Q1 and N_Q2 are the number of upper and lower
MOSFETs per phase, respectively; N_PHASE is the number of active
phases. The I_Q*VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW at
300kHz.
PVCC
BOOT
D
R_HI1
R_LO1
UGATE
C_GD
G
R_G1
R_GI1
C_GS
S
C_DS
Q1
PHASE
FIGURE 16. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
R_HI2
R_LO2
LGATE
C_GD
G
R_G2 ^RGI2
C_GS
S
D
C_DS
Q2
FIGURE 17. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the resistive
components along the transition path and in the bootstrap diode. The
portion of the total power dissipated in the controller itself is the power
dissipated in the upper drive path resistance (P_{DR_UP}), the lower drive
path resistance (P_{DR_UP}), and in the boot strap diode (P_BOOT). The rest
of the power will be dissipated by the external gate resistors (R_G1 and
R_G2) and the internal gate resistors (R_GI1 and R_GI2) of the MOSFETs.
Figures 16 and 17 show the typical upper and lower gate drives turn-on
transition path. The total power dissipation in the controller itself, P_DR,
can be roughly estimated as:
P_DR = P_{DR_UP} + P_{DR_LOW} + P_BOOT + (I_Q ⋅ VCC)
P_BOOT
=
P_{----Q----g---_---Q---1--}
3
P _{D R _UP}
=
⎛
⎜
⎝
------------^R----^H----^I--¹-------------
R_HI1 + R_EXT1
+
R^-----_L^---_O^---₁^{-R----+L---O--}R^--1--_E^---_X^----_T^--₁^--_{⎠⎟⎞}
⋅ -^P---^Q----^g---^_---^Q---¹--
3
P _{D R _LOW}
=
⎛
⎜
⎝
------------^R----^H----^I--²-------------
R_HI2 + R_EXT2
+
-_R----_L---_O---₂-^R----+^L---^O--_R--²--_E---_X----_T---₂-_{⎠⎟⎞}
⋅ ^P----^Q----^g---^_---^Q---²--
2
R_EXT1
=
R_G1
+
R_{-----G---I--1--}
N_Q1
R_EXT2
=
R_G2
+
R_{-----G---I--2--}
N_Q2
(EQ. 32)
Inductor DCR Current Sensing Component
Fine Tuning
MOSFET
DRIVER
V_IN
UGATE(n)
LGATE(n)
IL_n
L
DCR
INDUCTOR
V_L(s)
V_C(s)
R₁
C
V_OUT
C_OUT
ISL6328 INTERNAL CIRCUIT
R₂
ISENn-
I_n
+
-
ISENn+
V_C(s)
R_ISEN
I_SEN
FIGURE 18. DCR SENSING CONFIGURATION
Due to errors in the inductance and/or DCR it may be necessary
to adjust the value of R₁ and R₂ to match the time constants
correctly. The effects of time constant mismatch can be seen in
the form of droop overshoot or undershoot during the initial load
transient spike, as shown in Figure 19. Follow the steps below to
ensure the R-C and inductor L/DCR time constants are matched
accurately.
1. If the regulator is not utilizing droop, modify the circuit by
placing the frequency set resistor between FS and Ground for
the duration of this procedure.
2. Capture a transient event with the oscilloscope set to about
L/DCR/2 (sec/div). For example, with L = 1µH and
DCR = 1mΩ, set the oscilloscope to 500µs/div.
3. Record ΔV1 and ΔV2 as shown in Figure 19.
ΔV₂
ΔV₁
V_OUT
I_TRAN
ΔI
FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR
25
FN7621.1
June 7, 2011