ISL6328 Datasheet, PDF (23/33 Pages) Intersil Corporation – Dual PWM Controller For Powering AMD SVI Split-Plane Processors

ISL6328
It is recommended that the maximum current spike correspond
to an average sensed current level of 120µA. It is also
recommended that if the maximum current spike load was
applied to the Core regulator that overcurrent protection
shutdown initiate after 1ms. This would require a 0.01µF
capacitor be tied to the OCP pin. To calculate the OCP capacitor,
use Equation 22.
C_OCP
=
-²---⁰----^μ----^A-----^â‹---^t--^D----^E---^L---^A----^Y-
2V
(EQ. 22)
NORTHBRIDGE REGULATOR OVERCURRENT
The Northbridge regulator does not incorporate dual OCP. When
the sensed current of the Northbridge exceeds 100µA,
Overcurrent Protection Shutdown is initiated. The overcurrent
shutdown for the Northbridge regulator will only disable the
MOSFET drivers for the Northbridge. Once 7 retry attempts have
been executed unsuccessfully, the controller will disable UGATE
and LGATE signals for both Core and Northbridge and will latch
off requiring a POR of VCC to reset the ISL6328.
OVERCURRENT PROTECTION IN POWER SAVINGS
MODE
While in Power Savings Mode, the OCP trip point will be lower
than when running in Normal Mode and there is no
accommodation for current throttling. Equation 21, with N = 1,
will yield the OCP trip point for the Core regulator while in Power
Savings mode.
If an overcurrent event should occur while the system is in Power
Savings Mode, the ISL6328 will restart in the Normal state with
the PSI_L bit set to 1.
Individual Channel Overcurrent Limiting
The ISL6328 has the ability to limit the current in each individual
channel of the Core regulator without shutting down the entire
regulator. This is accomplished by continuously comparing the
sensed currents of each channel with a constant 170µA OCL
reference current. If a channel’s individual sensed current
exceeds this OCL limit, the UGATE signal of that channel is
immediately forced low, and the LGATE signal is forced high. This
turns off the upper MOSFET(s), turns on the lower MOSFET(s),
and stops the rise of current in that channel, forcing the current
in the channel to decrease. That channel’s UGATE signal will not
be able to return high until the sensed channel current falls back
below the 170µA reference.
General Design Guide
This design guide is intended to provide a high-level explanation of
the steps necessary to create a multiphase power converter. It is
assumed that the reader is familiar with many of the basic skills and
techniques referenced in the following. In addition to this guide,
Intersil provides complete reference designs that include
schematics, bills of materials, and example board layouts for all
common microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to determine
the number of phases. This determination depends heavily on
the cost analysis which in turn depends on system constraints
that differ from one design to the next. Principally, the designer
will be concerned with whether components can be mounted on
both sides of the circuit board, whether through-hole components
are permitted, the total board space available for power-supply
circuitry, and the maximum amount of load current. Generally
speaking, the most economical solutions are those in which each
phase handles between 25A and 30A. All surface-mount designs
will tend toward the lower end of this current range. If
through-hole MOSFETs and inductors can be used, higher
per-phase currents are possible. In cases where board space is
the limiting constraint, current can be pushed as high as 40A per
phase, but these designs require heat sinks and forced air to cool
the MOSFETs, inductors and heat-dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each MOSFET will
be required to conduct, the switching frequency, the capability of
the MOSFETs to dissipate heat, and the availability and nature of
heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is simple,
since virtually all of the loss in the lower MOSFET is due to current
conducted through the channel resistance (r_DS(ON)). In Equation
23, I_M is the maximum continuous output current, I_PP is the
peak-to-peak inductor current (see Equation 2), and d is the duty
cycle (V_OUT/V_IN).
P_{LOW, 1} =
r_DS(ON) ⋅
⎛
⎜
⎝
I_{--M---⎟⎞}
N⎠
2
⋅
(
1
–
d)
+
I_{--L---,---P2---P-----}⋅_---(_--1_{-----–-----}d_----)
12
(EQ. 23)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the dead
time when inductor current is flowing through the lower-MOSFET
body diode. This term is dependent on the diode forward voltage
at I_M, V_D(ON), the switching frequency, f_S, and the length of dead
times, t_d1 and t_d2, at the beginning and the end of the lower-
MOSFET conduction interval respectively.
P_{LOW, 2}
= V_D(ON) ⋅ f_S ⋅
⎛
⎜
I_--M---
⎝N
+
-^I-^P----^P- ⎟⎞
2⎠
⋅
t_d1
+
⎛
⎜
I_--M---
⎝N
–
I_{--P----P- ⎟⎞}
2⎠
⋅
t_d2
(EQ. 24)
The total maximum power dissipated in each lower MOSFET is
approximated by the summation of P_LOW,1 and P_LOW,2.
UPPER MOSFET POWER CALCULATION
In addition to r_DS(ON) losses, a large portion of the upper-MOSFET
losses are due to currents conducted across the input voltage
(V_IN) during switching. Since a substantially higher portion of the
upper-MOSFET losses are dependent on switching frequency, the
power calculation is more complex. Upper MOSFET losses can be
divided into separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode reverse-recovery
charge, Q_rr, and the upper MOSFET r_DS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does not
conduct any portion of the inductor current until the voltage at
the phase node falls below ground. Once the lower MOSFET
begins conducting, the current in the upper MOSFET falls to zero
as the current in the lower MOSFET ramps up to assume the full
inductor current. In Equation 25, the required time for this
23
FN7621.1
June 7, 2011