ISL6328 Datasheet, PDF (16/33 Pages) Intersil Corporation – Dual PWM Controller For Powering AMD SVI Split-Plane Processors

ISL6328
states are decoded with direction from the PWROK input as
described in the sections that follow. The ISL6328 uses a digital
to analog converter (DAC) to generate a reference voltage based
on the decoded SVI value. See Figure 7 for a simple SVI interface
timing diagram.
The upper and lower threshold levels for the SVI inputs are
programmable through the FS pin. The FS resistor can be tied to
either ground or to VCC. This option allows for selection of the
SVID threshold levels.
TABLE 1. SVID THRESHOLDS
FS RESISTOR TIED TO
SVI VIL (V)
SVI VIH (V)
VCC
0.55
1.05
Ground
0.45
0.85
Pre-PWROK METAL VID
At start-up, the controller decodes the SVC and SVD inputs to
determine the Pre-PWROK metal VID setting. Once the POR
circuitry is satisfied, the ISL6328 begins decoding the inputs per
Table 2. Once the EN input exceeds the rising enable threshold,
the ISL6328 saves the Pre-PWROK metal VID value in an
on-board holding register and passes this target to the internal
DAC circuitry.
TABLE 2. PRE-PWROK METAL VID CODES
SVC
SVD
OUTPUT VOLTAGE
(V)
0
0
1.1
0
1
1.0
1
0
0.9
1
1
0.8
The Pre-PWROK metal VID code is decoded and latched on the
rising edge of the enable signal. Once enabled, the ISL6328
passes the Pre-PWROK metal VID code on to internal DAC
circuitry. The internal DAC circuitry begins to ramp both the VDD
and VDDNB planes to the decoded Pre-PWROK metal VID output
level. The digital soft-start circuitry actually stair steps the
internal reference to the target gradually over a fixed interval. The
controlled ramp of both output voltage planes reduces in-rush
current during the soft-start interval. At the end of the soft-start
interval, the VDDPWRGD output transitions high indicating both
output planes are within regulation limits.
SVI Mode
Once the controller has successfully soft-started and VDDPWRGD
transitions high, the Northbridge SVI interface can assert PWROK
to signal the ISL6328 to prepare for SVI commands. The
controller actively monitors the SVI interface for set VID
commands to move the plane voltages to start-up VID values.
Details of the SVI Bus protocol are provided in the AMD Design
Guide for Voltage Regulator Controllers Accepting Serial VID
Codes specification.
Once the set VID command is received, the ISL6328 decodes the
information to determine which plane and the VID target
required. See Table 3. The internal DAC circuitry steps the
required output plane voltage to the new VID level. During this
time one or both of the planes could be targeted. In the event the
core voltage plane, VDD, is commanded to power off by serial VID
commands, the VDDPWRGD signal remains asserted. The
Northbridge voltage plane must remain active during this time.
If the PWROK input is de-asserted, then the controller steps both
VDD and VDDNB planes back to the stored Pre-PWROK metal VID
level in the holding register from initial soft-start. No attempt is
made to read the SVC and SVD inputs during this time. If PWROK
is reasserted, then the on-board SVI interface waits for a set VID
command.
VCC
SVC
1
2
3
456
7
8
9 10
11
12
SVD
ENABLE
PWROK
VDD and VDDNB
metal_VID
V_SVI
metal_VID
V_SVI
VDDPWRGD
FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP
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FN7621.1
June 7, 2011