ISL6328 Datasheet, PDF (13/33 Pages) Intersil Corporation – Dual PWM Controller For Powering AMD SVI Split-Plane Processors

ISL6328
Another benefit of interleaving is to reduce input ripple current.
Input capacitance is determined in part by the maximum input
ripple current. Multi-phase topologies can improve overall system
cost and size by lowering input ripple current and allowing the
designer to reduce the cost of input capacitance. The example in
Figure 2 illustrates input currents from a 3-phase converter
combining to reduce the total input ripple current.
The converter depicted in Figure 2 delivers 1.5V to a 36A load from
a 12V input. The RMS input capacitor current is 5.9A. Compare
this to a single-phase converter also stepping down 12V to 1.5V at
36A. The single-phase converter has 11.9A_RMS input capacitor
current. The single-phase converter must use an input capacitor
bank with twice the RMS current capacity as the equivalent
three-phase converter.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
1μs/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-CAPACITOR
RMS CURRENT FOR 3-PHASE CONVERTER
Figures 23, 24 and 25 in the section entitled “Input Capacitor
Selection” on page 28 can be used to determine the input-
capacitor RMS current based on load current, duty cycle, and the
number of channels. They are provided as aids in determining
the optimal input capacitor solution.
Active Pulse Positioning Modulated PWM
Operation
The ISL6328 uses a proprietary Active Pulse Positioning (APP)
modulation scheme to control the internal PWM signals that
command each channel’s driver to turn their upper and lower
MOSFETs on and off. The time interval in which a PWM signal can
occur is generated by an internal clock, whose cycle time is the
inverse of the switching frequency set by the resistor between the
FS pin and ground. The advantage of Intersil’s proprietary Active
Pulse Positioning (APP) modulator is that the PWM signal has
the ability to turn on at any point during this PWM time interval,
and turn off immediately after the PWM signal has transitioned
high. This is important because it allows the controller to quickly
respond to output voltage drops associated with current load
spikes, while avoiding the ring back affects associated with other
modulation schemes.
The PWM output state is driven by the position of the error
amplifier output signal, V_COMP, minus the current correction
signal relative to the proprietary modulator ramp waveform as
illustrated in Figure 3. At the beginning of each PWM time
interval, this modified V_COMP signal is compared to the internal
modulator waveform. As long as the modified V_COMP voltage is
lower then the modulator waveform voltage, the PWM signal is
commanded low. The internal MOSFET driver detects the low
state of the PWM signal and turns off the upper MOSFET and
turns on the lower synchronous MOSFET. When the modified
V_COMP voltage crosses the modulator ramp, the PWM output
transitions high, turning off the synchronous MOSFET and turning
on the upper MOSFET. The PWM signal will remain high until the
modified V_COMP voltage crosses the modulator ramp again.
When this occurs the PWM signal will transition low again.
During each PWM time interval, the PWM signal can only
transition high once. Once PWM transitions high, it can not
transition high again until the beginning of the next PWM time
interval. This prevents the occurrence of double PWM pulses
occurring during a single period.
To further improve the transient response, ISL6328 also
implements Intersil’s proprietary Adaptive Phase Alignment
(APA) technique, which turns on all phases together under
transient events with large step current. With both APP and APA
control, ISL6328 can achieve excellent transient performance
and reduce the demand on the output capacitors.
Adaptive Phase Alignment (APA)
When a load is applied, the output will fall in direct relation to the
amount of load being applied and the speed at which the load is
being applied. The ISL6329 monitors the output differentially
through the VSEN pin. If the sensed voltage drops quickly by a
user programmable magnitude (V_APATRIP), all of the upper
MOSFETs will immediately be turned on simultaneously. The trip
level is relative, not absolute, and can be programmed through a
resistor and capacitor tied in parallel from the APA pin to ground.
R_APA = ^V---₁-^A---_.-^P₇---^A-₅---^T-_μ--^R--_A-^I--^P--
(EQ. 4)
A 3900pF, X7R capacitor is required to be placed in parallel to
the APA resistor.
PWM Operation
The timing of each core channel is set by the number of active
channels. Channel detection on the ISEN2-, ISEN3- and ISEN4-,
pins selects 1-channel to 4-channel operation for the ISL6328.
The switching cycle is defined as the time between PWM pulse
termination signals of each channel. The cycle time of the pulse
signal is the inverse of the switching frequency set by the resistor
between the FS pin and ground (or VCC). The PWM signals
command the MOSFET driver to turn on/off the channel
MOSFETs.
The channel firing order for 4-channel operation, the channel
firing order is 1-2-3-4. For 3-channel operation, the channel firing
order is 1-2-3.
Connecting ISEN4- to VCC selects three channel operation. To set
2-channel operation, both ISEN4- and ISEN3- must be tied to
VCC. Similarly, to set single channel operation, ISEN4-, ISEN3-
and ISEN2- must be tied to VCC.
13
FN7621.1
June 7, 2011