ISL6328 Datasheet, PDF (11/33 Pages) Intersil Corporation – Dual PWM Controller For Powering AMD SVI Split-Plane Processors

ISL6328
Electrical Specifications Boldface limits apply over the operating temperature range. (Continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 6)
TYP
(Note 6) UNITS
POWER GOOD
Overvoltage Threshold
VSEN Rising
VDAC +
220mV
VDAC +
V
325mV
Undervoltage Threshold
VSEN Falling
VDAC -
345mV
VDAC -
mV
190mV
Power-Good Hysteresis
50
mV
OVERVOLTAGE PROTECTION
OVP Trip Level
OVP Lower Gate Release Threshold
V_DAC = 1.1V
SWITCHING TIME (Note 7) [See “Timing Diagram” on page 12]
1.75
1.79
1.85
V
0.35
V
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-On Non-overlap
LGATE Turn-On Non-overlap
GATE DRIVE RESISTANCE
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
SVI INTERFACE
t_RUGATE; V_PVCC = 8V, 3nF Load, 10% to 90%
26
ns
t_RLGATE; V_PVCC = 8V, 3nF Load, 10% to 90%
18
ns
t_FUGATE; V_PVCC = 12V, 3nF Load, 90% to 10%
18
ns
t_FLGATE; V_PVCC = 12V, 3nF Load, 90% to 10%
12
ns
t_PDHUGATE; V_PVCC = 12V, 3nF Load, Adaptive
10
ns
t_PDHLGATE; V_PVCC = 12V, 3nF Load, Adaptive
10
ns
V_PVCC = 12V, 15mA Source Current
V_PVCC = 12V, 15mA Sink Current
V_PVCC = 12V, 15mA Source Current
V_PVCC = 12V, 15mA Sink Current
2.5
Ω
2.0
Ω
1.6
Ω
1.1
Ω
SVC, SVD Input HIGH (VIH)
FS resistor tied to GND
0.85
V
SVC, SVD Input LOW (VIL)
SVC, SVD Input HIGH (VIH)
FS resistor tied to GND
FS resistor tied to VCC
1.05
0.45
V
V
SVC, SVD Input LOW (VIL)
SVD Low Level Output Voltage
FS resistor tied to VCC
510Ω Resistor to 1.8V
0.55
V
0.4
V
SVC, SVD Leakage (Note 7)
±5
µA
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Limits should be considered typical and are not production tested.
11
FN7621.1
June 7, 2011