ISL6328 Datasheet, PDF (22/33 Pages) Intersil Corporation – Dual PWM Controller For Powering AMD SVI Split-Plane Processors

ISL6328
In the event that during normal operation if the PVCC, VCC or
GVOT voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from any
more pre-POR overvoltage events.
Undervoltage Detection
The undervoltage threshold is set at VDAC - 300mV typical. When
the output voltage (VSEN-RGND) is below the undervoltage
threshold, PGOOD gets pulled low. No other action is taken by the
controller. PGOOD will return high if the output voltage rises
above VDAC - 250mV typical.
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or GND,
become open, the ISL6328 is designed to detect this and shut
down the controller. This event is detected by monitoring small
currents that are fed out the VSEN and RGND pins. In the event of
an open sense line fault, the controller will continue to remain off
until the fault goes away, at which point the controller will re-
initiate a soft-start sequence.
Overcurrent Protection
The ISL6328 takes advantage of the proportionality between the
load current and the average current, I_AVG, to detect an
overcurrent condition. See “Continuous Current Sampling” on
page 14 and “Channel-Current Balance” on page 15 for more
detail on how the average current is measured. Once the average
current exceeds 100µA, a comparator triggers the converter to
begin overcurrent protection procedures.
The overcurrent trip threshold is dictated by the DCR of the
inductors, the number of active channels, the DC gain of the
inductor RC filter and the R_ISEN resistor. The overcurrent trip
threshold is shown in Equation 21.
I_OCP
=
100 m A
⋅
-----^N------
DCR
⋅
-¹--
K
⋅
R_ISEN
–
-^V---^I--^N--₂---–--_â‹--^N-_L-----^⋅â‹---^Vf--_S-^O----^U---^T-
⋅
-^V---^O----^U---^T-
V_IN
(EQ. 21)
Where:
K
=
-------^R----²---------
R₁ + R₂
See “Continuous Current Sampling” on
page 14.
f_SW = Switching Frequency
Equation 21 is valid for both the Core regulator and the
Northbridge regulator. This equation includes the DC load current
as well as the total ripple current contributed by all the phases.
For the Northbridge regulator, N is 1.
During soft-start, the overcurrent trip point is boosted by a factor
of 1.35. Instead of comparing the average measured current to
100µA, the average current is compared to 135µA. Immediately
after soft-start is over, the comparison level changes to 100µA.
This is done to allow for start-up into an active load while still
supplying output capacitor in-rush current.
OVERCURRENT PROTECTION SHUTDOWN
At the beginning of overcurrent shutdown, the controller sets all
of the UGATE and LGATE signals low, puts PWM3 and PWM4 (if
active) in a high-impedance state, and forces VDDPWRGD low.
This turns off all of the upper and lower MOSFETs. The system
remains in this state for fixed period of 12ms. If the controller is
still enabled at the end of this wait period, it will attempt a soft-
start, as shown in Figure 14. If the fault remains, the trip-retry
cycles will continue until either the fault is cleared or for a total of
seven attempts. If the fault is not cleared on the final attempt,
the controller disables UGATE and LGATE signals for both Core
and Northbridge and latches off requiring a POR of VCC to reset
the ISL6328.
It is important to note that during soft-start, the overcurrent trip
point is increased by a factor of 1.35. If the fault draws enough
current to trip overcurrent during normal run mode, it may not
draw enough current during the soft-start ramp period to trip
overcurrent while the output is ramping up. If a fault of this type
is affecting the output, then the regulator will complete soft-start
and the trip-retry counter will be reset to zero. Once the regulator
has completed soft-start, the overcurrent trip point will return to
it’s nominal setting and an overcurrent shutdown will be initiated.
This will result in a continuous hiccup mode.
OUTPUT CURRENT, 50A/DIV
0A
OUTPUT VOLTAGE,
500mV/DIV
0V
3ms/DIV
FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE
Note that the energy delivered during trip-retry cycling is much
less than during full-load operation, so there is no thermal
hazard.
CORE REGULATOR OVERCURRENT
The ISL6328 features a Dual Overcurrent Protection (OCP)
feature on the Core that allows AMD processors to “throttle” the
load current beyond the normal OCP threshold for brief periods of
time. These current spikes occur when idle processor cores are
enabled. Dual OCP is not enabled until soft-start is complete.
When the Core average sensed current, I_AVG, exceeds 100µA,
the Core regulator does not immediately initiate overcurrent
protection shutdown. The ISL6328 will, instead, source an
amount of current out of the OCP pin that is equivalent to the
amount of sensed current that exceeds 100µA. A capacitor tied
between the OCP pin and ground will immediately begin
charging. If the voltage across the capacitor, and thus the voltage
on the OCP pin, exceeds 2V then the ISL6328 will immediately
initiate overcurrent protection shutdown. If I_AVG decreases to a
level below 100µA prior to the voltage on the OCP pin exceeding
2V, then the OCP pin is internally pulled to ground and the
voltage on the OCP capacitor is discharged. If, at any time, the
average sensed current exceeds 145µA, the ISL6328 will
immediately initiate overcurrent protection shutdown.
22
FN7621.1
June 7, 2011