CD1865 Datasheet, PDF (96/150 Pages) Intel Corporation – Intelligent Eight-Channel Communications Controller

CD1865 — Intelligent Eight-Channel Communications Controller
Even though not all of the CD1865 registers are intended to be read/write, there is no hardware
mechanism to prevent the user from writing to them. The registers should, in some cases, not be
written to by the host. See the individual register descriptions for details.
In the register map, the binary addresses are shown relative to the CD1865 address lines. In 16- and
32-bit systems, it is a common practice to connect 8-bit peripherals to only 1-byte lane. In 16-bit
systems, the CD1865 appears at every other address, that is, A0 in the CD1865 is connected to A1
in the host. In 32-bit systems, the CD1865 appears at every fourth address, that is, A0 in the
CD1865 is connected to A2 in the host. In both of these cases, the addresses used by a programmer
are different than what is shown.
For instance, in a 16-bit Motorola 68000-based system (or other ‘big-endian’ processors), the
CD1865 is placed on data lines D0–D7 that are at odd addresses in the Motorola manner of
addressing. The A0 in the CD1865 is connected to A1 of the 68000. Thus, the CD1865 address $40
becomes $81 to a programmer. It is ‘left-shifted’ one bit, and A0 must be ‘1’ for low-byte (D0–D7)
accesses.
In a 16-bit Intel system (or other ‘little-endian’ processors), the CD1865 is again placed on data
lines D0–D7, but these are at even addresses. The A0 in the CD1865 is connected to the A1 in the
host, but the host’s A0 must be a ‘0’ to access data lines D0–D7.
Many 32-bit processors have internal logic to ‘steer’ the data to the correct pins regardless of
address value. However, if the processor employed does not, a scheme similar to the one described
for 16-bit machines can be used, except that the CD1865 addresses are shifted 2 bits instead of one.
Table 9. Register Summary (Sheet 1 of 2)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Global Registers
GFRCR
SRCR
PPRH
PPRL
MSMR
TSMR
RSMR
GSVR
SRSR
MRAR
TRAR
RRAR
GSCR1
GSCR2
GSCR3
CAR
PkgTyp
User
Defined
ILV[1]
User
Defined
User
Defined
User
Defined
Reserved
RegAckEn
User
Defined
ILV[0]
User
Defined
User
Defined
User
Defined
Reserved
Firmware Revision Code
DaisyEn
GlobPri
UnFair
Reserved
Binary Value
Binary Value
Binary Value
Binary Value
Binary Value
User
Defined
User
Defined
User
Defined
IT2
RREQext RREQint TREQext TREQint
Modified Interrupt Vector Provided On Read
Modified Interrupt Vector Provided On Read
Modified Interrupt Vector Provided On Read
User
Defined
C2
C1
C0
User
Defined
C2
C1
C0
User
Defined
C2
C1
C0
Reserved Reserved
A7(0)
C2
Bit 1
AutoPri
IT1
MREQext
User
Defined
User
Defined
User
Defined
C1
Bit 0
PriSel
IT0
MREQint
User
Defined
User
Defined
User
Defined
C0
96
Datasheet