CD1865 Datasheet, PDF (69/150 Pages) Intel Corporation – Intelligent Eight-Channel Communications Controller

Intelligent Eight-Channel Communications Controller — CD1865
For details on transmitter flow-control operation, refer to the Section 7.3 on page 72.
Figure 24. Transmitter Operation
TRANSMITTER
FIFO
TRANSMITTER HOLDING REGISTER
TRANMSITTER SHIFT REGISTER
FULL /
EMPTY
BIT
BACKGROUND CODE:
FIFO-TO-H.R. TRANSFER, FLOW
CONTROL, OTHER FEATURES
(POLLING LOOP)
FOREGROUND CODE:
BIT DISASSEMBLY,
H.R.-TO-S.R. TRANSFER
(INTERRUPT-DRIVEN)
RTS
OUT
CTS
IN
7.2.2
7.2.3
FIFO Operation
An 8-byte FIFO is provided for each transmit channel. In addition to the 8-byte FIFO, the CD1865
also contains a Transmit Holding register and the Transmit Shift register for each channel.
However, when servicing a Transmit Service Request, only up to eight characters can be written
into the Transmit Data register (TDR) consecutively.
Transmit Service Requests
Generating a Transmit Service Request depends on control bits in the Enable register (). Setting the
TxRdy bit of the specifies that a Transmit Service Request be generated when the FIFO is empty.
When this condition occurs, there is still one character in the Transmit Holding register and another
character in the Transmit Shift register. The host CPU, therefore, has up to two-character times to
respond before the transmitter output goes into the idle (Mark) condition.
Setting the TxMpty bit instead of the TxRdy bit of the specifies that a Transmit Service Request be
generated only when the FIFO, the Transmit Holding register, and the Transmit Shift register are
empty. When this condition occurs, it means that all characters are completely transmitted and the
channel can now be re-configured. It is recommended that one of the two bits be set as needed, but
do not set both bits at the same time.
End of a service request must be signalled to the CD1865 by writing to the End Of register ().
Datasheet
69