CD1865 Datasheet, PDF (87/150 Pages) Intel Corporation – Intelligent Eight-Channel Communications Controller

Intelligent Eight-Channel Communications Controller — CD1865
not less than 1.0 milliseconds. As shown in the Internal Operation Flow Chart, Figure 4 on page 25,
processing timer events is in the outer (lowest priority) loop of the CD1865 firmware. A timer tick
that is too short may result in two ticks occurring within one pass through the outer loop; this
would result in missing one tick. This is not fatal, but it would result in inaccurate timings.
8.8
Channel Initialization and Changes
Prior to enabling the individual channels, program the Channel registers with required channel
options and parameters such as character lengths, parity type, Receive FIFO thresholds, modem
signal detection levels, bit rates, and so on. When ready to begin, enable service requests.
Channel initialization is accomplished by first writing to the CAR register with the number of the
channel to be programmed. This channel number automatically becomes part of the address for
subsequent channel register programming. The host can use the same set of register addresses for
all channels, thus eliminating the need to calculate addresses.
Certain channel options are controlled by the three Channel Option registers. All changes to the
Channel Option registers must be accompanied by setting the appropriate Channel Option register
‘changed’ bits in the Channel Command register (CCR). The CD1865 processor regularly samples
the CCR for any value that is not a ‘0’. If the CCR is not a ‘0’, the CD1865 decodes the command
or commands, acts on them, and clears the CCR to signify completion of the commands. New
commands must not be issued until any existing commands have been completed.
8.9
Transmitting Data
When transmitting data, a service request is received when the Transmit FIFO is empty. The
number of the channel requesting service (for example, the one with the empty FIFO) is available
from the GCR. If there is more data to be sent, transfer up to 8 bytes to the FIFO. If no data is
available, disable the channel. The easiest way to accomplish this is by clearing the appropriate bit
in the Enable register (). When new data is available, re-enable the channel by the , and a new
service request for transmit data is received. At that time, transfer the data to the FIFO. Channels
can be enabled or disabled by giving enable and disable commands by the Channel Command
register (CCR), but it is a slower process.
In some cases, it is necessary to know when a channel has sent the last bit of the last character
rather than an empty FIFO. One example would be when changing bit rates. Two bits in the Enable
register (), TxMpty and TxRdy, control the exact conditions for generating a service request.
TxRdy indicates when the FIFO is empty, and TxMpty indicates when the last bit has been sent. It
is acceptable to have both bits set but proper operation is achieved by switching from the FIFO
empty status to the transmitter empty status when it is necessary to know that all data has been
completely sent. If they are set, the FIFO Empty Service Request always occurs first. If there is no
more data to be sent, the Transmitter Empty Service Request is received later, but in the mean time,
FIFO empty requests may also be received. Once the last bit of the last character has been sent, a
channel can be reconfigured.
Datasheet
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