CD1865 Datasheet, PDF (137/150 Pages) Intel Corporation – Intelligent Eight-Channel Communications Controller

Intelligent Eight-Channel Communications Controller — CD1865
All times are based on a master clock (CLK) of 15 MHz. All times are measured in nanoseconds.
Intel-style handshake signals (where appropriate) are shown in {curly brackets}.
Table 11. Unclocked Timings (Sheet 1 of 2)
Number
Description
t₁
Setup time, Address to CS*, DS* {CS*, RD* or WR*}
t₂
Setup time, R/W* to CS* or DS*
t₃
Hold time, Address after CS* or DS* {CS* or RD* or WR*}
t₄
R/W* hold time after CS* and DS*
Delay time, DTACK* assert to valid Read Data:
t₅
If DTACKDLY = 0
If DTACKDLY = 1
DTACK* assert after CS* or DS* {RD*} or ACKIN*
t₆
If DTACKDLY = 0
If DTACKDLY = 1
t₇
Hold time, Read Data after CS* and DS*{RD*} high
CS* or DS* {RD*} high from DTACK* low
t₈
If DTACKDLY = 0
If DTACKDLY = 1
t₉
DTACK* inactive from (CS* or ACKIN*) or DS* high
t₁₀
DS* {RD*} high pulse width
t₁₁
Setup time, Address to ACKIN*
t₁₂
Setup time, Write Data to DS* {or WR*} low
t₁₃
Hold time, Write Data after DS* {or WR*} high
t₁₄
x_REQ* deassert after DTACK* asserted
t₁₅
Setup time, R/W* {WR*} and CS* to ACKIN* low
t₁₆
x_REQ* reassert delay after write to EOSRR
t₁₇
ACKIN* assert/deassert to ACKOUT* assert/deassert prop delay
t₁₈
Data bus out of high-impedance after DS* {RD*} low
t₁₉
Setup time, Address to DS* {RD*} during acknowledge cycles
MIN1
3
0
0
3
1
25
1
5
10
0
0
3
4
MAX1
Notes
2
2
3, 4
3, 4
25
-12
75
2, 5
85
12
3, 6, 7
4, 4., 8, 7
12
3, 9, 4
4
10, 11
0
2^Tclk+30
2^Tclk+30
15
12
13
14, 15
16
Datasheet
137