CD1865 Datasheet, PDF (88/150 Pages) Intel Corporation – Intelligent Eight-Channel Communications Controller

CD1865 — Intelligent Eight-Channel Communications Controller
8.10
8.11
8.11.1
8.11.2
Receiving Data
When receiving data, a service request is sent (for Good Data) when either the number of received
bytes meets the threshold level, the Receive Time-out expires, or there is Good Data followed by a
Receive Exception Condition (the CD1865 must transfer all the Good Data before giving the
Exception). In all cases, the service-request routine reads the channel number requesting service
(from GCR) and the number of bytes available (which can be more, the same, or less than the
number set as the threshold) from the Receive Data Count register (RDCR), and proceeds to
transfer that many bytes, if possible.
It is not necessary to transfer as many bytes as are available or any bytes at all. If the host’s buffer
is nearly or completely full, the host can accept only those bytes it has room for, disable Receive
Service Requests, exit the Service Request Routine, process the buffer, enable Receive Service
Requests, and wait for the next service request. If no bytes are transferred during a Receive Service
Request, and Receive Service Requests are still enabled, the CD1865 immediately re-requests
service because the internal conditions that caused the request to be issued are still true. The host
may either disable service requests or suspend host service request processing; however, both of
these options should be implemented carefully as suspending service requests may result in an
overflow condition if the suspension lasts too long.
Programming Examples
When writing programs for the CD1865 evaluation board, a few guidelines should be followed to
keep the programs from getting lost or error conditions to be encountered. This section discusses
some programming errors and ways to avoid them.
Programming the Service Match Registers
One common programming error is made when using the CD1865 in the area of Service Match
registers (SMR). The value placed in these three registers during chip initialization must exactly
match the value that is present on the address inputs A0–A6 during the service acknowledge cycle.
(When the ACKIN* control signal is activated.) If this condition is not met, the CD1865 does not
respond with a DTACK* to terminate the bus cycle. This causes the system to hang.
CD1865 Initialization
Initializing the CD1865 is simple and quite straight forward. This section presents some guidelines
for the sequence to write to the various registers to correctly complete the initialization process.
Refer to Section 8.4 on page 84 for a flow-chart style description of the process.
The first step in the initialization process is to issue a master reset command to the CD1865 internal
logic. This can be done in one of the two ways: throughout the use of the RESET* control signal at
the hardware level, or via the chip reset command at the software level. The software reset
command is issued by placing a value of x’81 in the CCR register. Internally the chip reset
command does the same thing as activating the RESET* control input. The internal micro-code
enters the exact same routines to setup the chip for operation. When the reset command has been
issued, the program must wait until the GSVR has a value of x’FF. Until this value is placed in the
GSVR by the micro-code, the CD1865 initialization procedures are not complete.
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Datasheet