CD1865 Datasheet, PDF (18/150 Pages) Intel Corporation – Intelligent Eight-Channel Communications Controller

CD1865 — Intelligent Eight-Channel Communications Controller
5.0
Functional Description
5.1
Introduction
The CD1865 I/O coprocessor controls eight full-duplex channels that transfer data at rates up to
115.2 kbps. The CD1865 efficiently moves data between the serial channels and the host, resulting
in a great improvement in system-level throughput and a reduction in overhead on the host CPU.
This improvement is obtained by reducing the number of service requests (interrupts) the host must
respond to and reducing the complexity and time required to handle each service request.
The CD1865 relies on a combination of features to reduce the number and complexity of service
requests. Most important are the buffers for transmit and receive data. Each serial channel has three
8-byte FIFOs — one each for transmit, receive, and receive-exception status. The Receive FIFOs
have programmable thresholds to minimize interrupt latency requirements. The vectored service
requests and the Good Data interrupt allow the host system to immediately transfer data upon
beginning processing of a service request, without tedious checking of flags and error conditions.
The CD1865 is based on a high-performance, proprietary RISC processor architecture developed
by Intel specifically for data communications applications. The CD1865 processor executes all
instructions in one-clock cycle, and it uses a register window architecture to ensure zero-overhead
context switch for each type of internal interrupt. The instruction set of this processor is optimized
for bit-oriented tasks that combined with instantaneous response to sending or receiving one bit,
allow highly efficient processing of characters. All firmware for the CD1865 processor is
contained in an on-device ROM, and requires no user programming.
The CD1865 processor is assisted in its task by specialized peripheral logic. Serial data
transmission and reception is handled by ‘bit engines’. Each channel has a bit engine for
transmitting and another for receiving. While each engine handles all bit-level timing, bit-to-
character assembly is done in firmware. Bits are passed to the CD1865 processor by internal
interrupts over a special bus dedicated to this purpose. Special internal-interrupt context hardware
reduces overhead on internal interrupts to zero by pointing to the correct register window for every
possible context, and a unique Global Index register eliminates address calculations by always
pointing to the current channel. External service requests to the host system are also hardware
assisted. There is a queue for each of the three classes of external service requests, and the request/
acknowledgment mechanism is entirely in hardware to minimize response time.
The CD1865 processor assembles bits into characters, checks parity and formatting parameters,
and stores the data in the FIFOs as required. FIFOs are maintained as RAM-based structures, and
both the local CD1865 processor and the host access them by Pointer registers by an Indexed
Addressing mode.
The CD1865 communicates with the host by service requests and service acknowledgments.
Service requests can be handled either as interrupts or by polling. Regardless of the method used,
the CD1865 has features to minimize both the number of requests to be serviced and the time
required to service them. The number of service requests is reduced by the FIFOs since a service
request is required only every eight characters. To reduce the time required per request, the
CD1865 supplies separate vectors for four different types of service requests. This reduces the time
required by the host CPU to determine what action to take. For example, there is a unique vector
for Good Data so that the host wastes no time checking status bits for error conditions. If there is an
error condition, the CD1865 supplies a unique vector pointing to the error-handling routine. Other
vectors report transmit status and modem signal change.
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Datasheet