CD1865 Datasheet, PDF (89/150 Pages) Intel Corporation – Intelligent Eight-Channel Communications Controller

Intelligent Eight-Channel Communications Controller — CD1865
The next function to be performed is global initialization. These steps set up the chip ID for the
CD1865, the Service Match registers (SMR) for the three service request levels and the Prescaler
Period register. The SMR should be programmed as discussed previously (Section 8.1). The
Prescaler Period register value (high and low) sets the basic time scale for internal timer operation,
such as the receiver time-out period. A value must be chosen that yields a timer period of no less
than 0.1 ms.
Following global initialization, each channel must be programmed for the desired mode of
operation, including the transmit and receive baud rate divider constants, the individual character
settings such as parity, bits per character, and number of Stop bits. Receive FIFO threshold levels,
special character values, modem output signal levels and interrupt conditions. Before beginning the
process of channel initialization, the CAR register must be loaded with the number of the register
to be worked on. One important point to remember is that before placing a new value in any of the
COR registers or issuing the COR change command, the CCR must be checked to be sure that it
has a value of zero. If it is not zero, then the CD1865 may be processing a previous CCR command
and the CCR and the CORs must be changed.
If the program is ready at this point to respond to interrupts then the appropriate interrupt condition
bits for transmit and receive can be set in the SRER, and the transmitter and receiver can be
enabled by command to the CCR.
The following sections explain the initialization sequence.
Global Initialization
Use Set_Byte to write to the register, and Read_Byte to read the register content. For details on the
two functions, refer to the following basic I/O operations.
Set_Byte(GSVR, 0x00);
// Clear GSVR for chip reset
Wait_CCR();
// Confirm CCR is clear
Set_Byte(CCR, 0x81);
// Reset all Command
Wait_GSVR();
// wait to be FF
Set_Byte(PPRH, 0x80 );
// Set up Timer Prescaler (High)
Set_Byte(PPRL, 0xe8 );
// Set up Timer Prescaler (Low)
/*-------------------------------------------------------------------------
/* set up the Service Match Register according to the decoding ACKIN value
/* In this case, we decoded to be 0x8x.
/*-------------------------------------------------------------------------*/
Set_Byte(RX_SMR, 0x8a );
// Set Service Match reg.
Set_Byte(TX_SMR, 0x85);
Set_Byte(MDM_SMR, 0x81);
// comment out the following line if is using
the hardware acknowlegement.
//Set_Byte(SRCR, 0x40);
// Set up the software interrupt acknowledge
Channel Initialization
Set_Byte(CAR, chan);
Set_Byte(COR1, 0x03);
Set_Byte(COR2, 0x00);
Set_Byte(COR3,0x35);
Wait_CCR();
Set_Byte(CCR, 0x4e);
Set_Byte(SCHR1, 0x11);
Set_Byte(SCHR2, 0x13);
Set_Byte(SCHR3, 0x11);
// Setup channel access register to be the
// Specified channel number.
// No parity, 8-bit char, 1-stop bit
// Disable all COR2 functions
// Special char detection, FCT
// XON defined (cntl-Q 0x11)
// XOFF defined (cntl-S 0x13)
Datasheet
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