CD1865 Datasheet, PDF (48/150 Pages) Intel Corporation – Intelligent Eight-Channel Communications Controller

CD1865 — Intelligent Eight-Channel Communications Controller
Figure 16.
NO_OSC
OSC1
OSC2
DBLCLK
CLK
FROM RESET LOGIC
D
Q
RQ
CKOUT
6.2.3
6.2.4
1× Clock Option
It is recommended that a 2×-clock option be used where ever possible. If using a 1×-clock options,
refer to Table 10 on page 129 for clock duty cycle requirements.
Bit Rate Options
The CD1865 supports independent transmitter and receiver bit rates on each of its eight channels.
The bit rate is determined by a 16-bit period value (divisor) stored in the Transmitter Bit Rate
Period registers (TBPRH and TBPRL), or in the Receiver Bit Rate Period registers (RBPRH and
RBPRL). These registers establish the period of the corresponding Transmitter and Receiver Bit
Rate counters. To set a given bit rate, the value to be loaded is determined by the following
equation:
Bit Rate Divisor = ₍--₁---₆-----_x----_d---_e---⁽_s---^Ci--_r-^L-_e---^Kd-----_Bf--^r--_ie-_t--^q-_R--^u--_a-^e--_t-ⁿ-_e---^c-_{--^yi--_n--^{--ⁱ-_b-ⁿ--_i-_t-^H-_s---^e--_p-^r--_et--^z-_r--^}-_s-⁾--_e---_c---_o----_n---_d---_}--₎
This equation may yield a non-integer result. The nearest integer value is the optimum choice for
that bit rate and system clock combination. The value loaded in the Bit Rate Period registers must
be that integer expressed as a 16-bit binary value. If rounding is necessary, the percentage bit rate
error can be calculated by:
(Bit Rate Divisor – Integer) × 100 ⁄ Bit Rate Divisor
The popular bit rates and their corresponding divisors at various system clock rates are shown in
Table 5.
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Datasheet