CD1865 Datasheet, PDF (58/150 Pages) Intel Corporation – Intelligent Eight-Channel Communications Controller

CD1865 — Intelligent Eight-Channel Communications Controller
7.0
Serial Interfaces
7.1
Receiver Operation
7.1.1
Basic Operation
All receivers are disabled upon master reset. To prepare a receiver, first initialize and then enable it.
Once initialized and enabled, the receiver monitors the RxD Line and waits for a high-to-low
transition, which indicates a Start bit. This sampling is performed at one-eighth of the System-
clock rate regardless of the Programmed bit rate, and it provides accuracy of synchronization with
the incoming data. See Figure 21 below for CD1865 bit synchronization. Once a transition is
detected, the receiver checks the RxD Input state again (a half-bit time later) to validate that it is a
Start bit. A valid Start bit is defined a ‘space’ or a logic ‘0’. If the RxD Input is no longer a ‘space’,
then a false Start bit is assumed and the receiver resumes the search for a high-to-low transition. If
a valid Start bit is detected, the RxD Input is sampled at one-bit time intervals in the middle of the
bit to ensure stable data. Characters are assembled according to the programmed content of the
Channel Option register (COR1). Valid character framing (presence of a Stop bit), and Optional
Parity bits are checked. After a character is assembled, it is placed in a temporary Holding register.
Then the CD1865 processor checks for error conditions, FIFO overrun, and special character
match before placing the character and its corresponding status into the Receive and Status FIFOs.
7.1.2
Receive FIFO Operation
Eight bytes of FIFO are assigned to each receiver for data storage, in addition to the Receive
Holding register and the Receive Shift register. Once the number of data bytes received and stored
in the FIFO reaches a programmed threshold, the CD1865 can be programmed to generate a
service request. See Figure 22 on page 59 for Receive Operation. The Receive FIFO Service
Request threshold can be selected by programming the RxTH bits 3:0 in the Channel Option
register 3. A service request threshold of one-to-eight characters can be selected. Once this
threshold is defined, a service request is automatically triggered when the condition is met. It is
possible that by the time the host responds to the service request, there is more data in the FIFO
than the threshold level.
Figure 21. Bit Synchronization in CD1865
SAMPLES AT
1/8-SYSTEM
CLOCK
full-bit full-bit full-bit full-bit
time
time
time
time
full-bit full-bit
time
time
full-bit full-bit full-bit
time
time
time
Start
1/2-bit
Bit Detect time
58
Datasheet