CD1865 Datasheet, PDF (53/150 Pages) Intel Corporation – Intelligent Eight-Channel Communications Controller

Intelligent Eight-Channel Communications Controller — CD1865
A bus cycle consists of two half-clock periods. During the clock-low period, the transaction is set
up internally, and the local bus arbitration occurs. During the clock-high period, the read or write
transaction to RAM occurs. On write cycles, the data from the host is latched internally on the low-
to-high clock transition. On read cycles, the data is available shortly after the end of the clock-high
period.
Read and write cycles differ slightly in timing; during a write, it is permissible to remove the WR*
or DS* relatively early during the high-clock period, however, this cannot be done during read
cycles. The RD* or DS* Strobe is used as an output enable, and must remain low for the data to
appear on the external data bus.
Service request acknowledgment cycles follow a different timing than ordinary read cycles. First, it
is necessary to have the address stable before asserting ACKIN*. Second, the setup time from
ACKIN* and DS* (or RD*) going low to the falling clock edge is longer due to additional internal
logic involved in service request acknowledge cycles.
Figure 17. Typical Unclocked Bus Interface
A[0:6]
R/W*
CS*, DS*
DB[0:7]
DTACK*
Datasheet
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