CD1865 Datasheet, PDF (129/150 Pages) Intel Corporation – Intelligent Eight-Channel Communications Controller

Intelligent Eight-Channel Communications Controller — CD1865
Service Acknowledge Cycles are a special case of read cycles. The service acknowledge ‘read’
(which returns the Global Service Request Vector value to the host) is started when the read/write
state machine detects both DS* and another internal signal derived from both ACKIN* and DS*.
There are two possible worst-case paths to consider when determining whether DS* and ACKIN*
meet the necessary setup times to guarantee recognition on a particular clock edge. The longest
path is DS*; it must propagate through a gate, an 8-bit comparator, a state machine, and another
gate before arriving at the read/write state machine. The setup time for this is given in Table 10.
The other critical path is ACKIN*; it must pass through a state machine and a gate before arriving
at the read/write state machine. The setup time to guarantee recognition on a particular clock edge
is given in Table 10. Intel-style pin names are shown in {brackets}. All times are in nanoseconds,
unless otherwise specified.
Table 10. Clocked Timings (Sheet 1 of 2)
Number in
Figures
t₁
t₂
t₃
t₄
t₅
t₆
t₇
t₈
t₉
t₁₀
t₁₁
t₁₂
t₁₃
t₁₄
t₁₅
t₁₆
t₁₇
Description
Setup, DS*{RD*} and CS* low to CLK low, for read or write cycle to start
(‘ordinary’ reads and all writes)
Setup, DS* {RD*} low to CLK low, for service acknowledge cycle to start
(ACKIN* cycles and read cycles from acknowledge registers)
Setup, ACKIN* low to CLK low for cycle to start
Setup, Address valid to CS* and DS* low
Setup, Address valid to DS* (service acknowledge cycles)
Setup, Write Data valid to CLK high
Setup, R/W* {RD*, WR*} stable to DS* and CS* low (read, write cycles)
(DS* and CS*), or (RD* and CS*), or (WR* and CS*), high
Hold time, CS* low after CLK high (read, write cycles)
Hold time, DS* {RD*} after valid data
Hold time, Address valid after CLK high
Hold time, Write Data valid after CLK high
Hold time, ACKIN* low after next CLK low
Clock Period (T_CLK)
Clock low time
Clock high time
Clock duty cycle (50% ± 10%)
Clock rise/fall time
t₁₈
RESET pulse width (after power is good and clock is stable)
t₁₉
Data Bus out of Hi-Z after CLK low
t
20
Read Data valid after CLK high
t₂₁
ACKIN* to ACKOUT* propagation delay
t
22
ACKOUT* high after ACKIN* high
t₂₃
DS* {RD*} high to data bus three-state
t₂₄
DTACK* assert after CLK high (DTACKDLY = 0)
t₂₅
DTACK* assert after CLK low (DTACKDLY = 1)
MIN (1)
10
15
10
3
4
0
0
5
5
0
15
10
4
30
12
12
5 clock
periods
0
0
MAX (1)
Infinity
200
3
35
12
12
10
25
20
Notes
2
3
4
2, 5
6, 7
8
8
8
9
10
10
10
11
12
Datasheet
129