82595TX Datasheet, PDF (9/59 Pages) Intel Corporation – ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER

82595TX
2 2 PCMCIA Bus Interface (Continued)
Symbol
Pin
No
Type
Name and Function
OE
14
I
OUTPUT ENABLE (Memory Read) Active low
WE
15
I
WRITE ENABLE (Memory Write) Active low
IORD
18
I
IO READ Active low
IOWR
19
I
IO WRITE Active low
IOIS16 40
O IO IS 16 Active low output which indicates that an IO cycle access to the
82595TX solution is 16-bit wide IOIS16 should be asserted prior to Card
Enable or CMD (IORD or IOWR) assertion
WAIT
37
O WAIT Active low output when driven low extends host cycles to the 82595TX
IREQ
26
O 82595TX INTERRUPT Active low output
RESET 12
I
RESET Active high reset signal
CE1
81
I
Card Enable 1 and Card Enable 2 active low signals driven by the host
CE2
82
These signals provide a card select based on an address decode (decode
done by the host) and also byte lane enables When both CE1 and CE2 are
high no host accesses are made to the card If CE1 is low (active) and CE2 is
high (inactive) the device operates in byte access mode with valid data being
driven on D0–D7 and A0 determines the selection of an odd or even byte
When both CE1 and CE2 are low a word access is taking place In this case
A0 is ignored and the data is transferred on D0 – D15 Odd-byte-only accesses
can occur when CE1 is high and CE2 is low In this case the data is driven on
D8–D15 and A0 is ignored See Section 4 9 for a summary of the PCMCIA
decode functions
REG
80
I
REG is an active low input used to determine whether a host access is to
Attribute memory (the 1st 1K of FLASH or CONF Regs) or to Common
memory (FLASH above 1K) If REG is low the access is to Attribute memory if
REG is high the access is to Common memory REG is also asserted low for
all accesses to the 82595TX’s IO Registers (including the access to the local
DRAM via the 82595TX’s Local Memory IO Port) See Section 4 9 for a
summary of the PCMCIA decode functions
EVENT 32
O EVENT is an active low output which when enabled will be asserted
whenever a frame has been received by the 82595TX This allows the
82595TX to ‘‘wake up’’ a system which has powered down (with the exception
of powering down the LAN) This output will remain asserted until the
82595TX’s RCV Interrupt (for the frame which woke up the system) has been
acknowledged
2 3 Local Memory Interface
Symbol
Pin
No
Type
Name and Function
MADDR0 126 O LOCAL MEMORY ADDRESS (MADDR0 – MADDR8) These outputs contain
MADDR1 127
the multiplexed address for the local DRAM
MADDR2 128
MADDR3 129
MADDR4 130
MADDR5 132
MADDR6 133
MADDR7 134
MADDR8 135
9