82595TX Datasheet, PDF (16/59 Pages) Intel Corporation – ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER

82595TX
written into the 82595TX’s Local Memory IO Port
then transferred to the DRAM by the 82595TX be-
tween CPU cycles This prefetch mechanism of the
82595TX allows for IO read and writes to the local
memory to be performed with no additional wait-
states (3 clocks per data transfer cycle)
The DMA unit provides addressing and control to
move RCV or XMT data between the 82595TX and
the local DRAM For transmission the CPU is re-
quired only to copy the data to the local memory
initialize the 82595TX’s DMA Current Address Reg-
ister (CAR) to point to the beginning of the frame
and issue a Transmit Command to the 82595TX
The DMA unit facilitates the transfers from the local
memory to the 82595TX as transmission takes
place The DMA unit will reset upon collision during
a transmission enabling automatic re-transmission
of the transmit frame During reception the DMA
unit implements a recyclable ring buffer structure
which can receive continuous back to back frames
without CPU intervention on a per frame basis (see
Section 8 2 for details)
The 82595TX provides address decoding and con-
trol to allow access to an external Boot EPROM
FLASH or an IA PROM if these components are uti-
lized in an 82595TX design (an IA PROM cannot be
used for Plug N’ Play) The 82595TX also provides
two complete interfaces to a serial EEPROM (Port1
or Port2) to replace jumper blocks used to contain
configuration information Port1 is used to store con-
figuration information such as IO Mapping Window
Interrupt line selection etc and is backwards pin
compatible to the 82595TX EEPROM interface
Port2 is used to store configuration information as in
Port1 in addition it is used to store Plug N’ Play
information as defined in the Plug N’ Play Specifica-
tion
The 82595TX arbitrates accesses to the local mem-
ory sub-system by the CPU and the 82595TX The
arbitration unit will hold off an 82595TX DMA cycle
to the local memory if a CPU cycle is already in prog-
ress Likewise it will hold off the CPU if an 82595TX
cycle is already in progress The cycle which is held
off will be completed on termination of the preceding
cycle
3 3 CSMA CD Unit
The CSMA CD unit implements the IEEE 802 3
CSMA CD protocol It performs such functions as
transmission deferral to link traffic interframe spac-
ing exponential backoff for collision handling ad-
dress recognition etc The CSMA CD unit serves as
the interface between the local memory and the se-
rial interface It serializes data transferred from the
local memory before it is passed to the serial inter-
face unit for transmission During frame reception it
converts the serial data received from the serial in-
terface to a byte format before it is transferred to
local memory The CSMA CD unit strips framing pa-
rameters such as the Preamble and SFD fields be-
fore the frame is passes to memory for reception
For transmission the CSMA CD unit builds the
frame format before the frame is passed to the serial
interface for transmission
3 4 Serial Interface
The 82595TX’s serial interface provides either an
AUI port interface or a Twisted Pair Ethernet (TPE)
interface The AUI port can be connected to an
Ethernet Transceiver cable drop to provide a fully
compliant IEEE 802 3 AUI interface The AUI port
can also interface to a transceiver device to
provide a fully compliant IEEE 802 3 10BASE2
(Cheapernet) interface The TPE port provides a ful-
ly compliant 10BASE-T interface The 82595TX au-
tomatically enables either to the AUI or TPE inter-
face depending on which medium is connected to
the chip Software configuration can override this
automatic selection
4 0 ACCESSING THE 82595TX
All access to the 82595TX is made through one of
three banks of IO registers Each bank contains 16
registers Each register in a bank is directly accessi-
ble via addressing Through the use of bank switch-
ing the 82595TX utilizes only 16 IO locations in the
host system’s IO map to access each of its regis-
ters The different banks are accessed by setting the
POINTER field in the 82595TX Command Register
to select each bank The Command Register is Reg-
ister for each bank
4 1 82595TX Register Map
The 82595TX registers are contained in three banks
of 16 IO registers per bank These three banks are
shown in the following three pages
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