82595TX Datasheet, PDF (54/59 Pages) Intel Corporation – ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER

82595TX
11 10 Serial Timings
Table 11-15 TPE Timings
Symbol
Parameter
Min
Typ
Max
Unit
t₉₀
Number of TxD Bit Loss at Start of Packet
2
bits
t₉₁
Internal Steady State Propagation Delay
400
ns
t₉₂
Internal Start UP Delay
600
ns
t₉₃
TDH and TDL Pairs Edge Skew ( V_CC 2)
15
3
ns
t₉₄
TDH and TDL Pairs Rise Fall Times
( 0 5V to V_CC ^b 0 5V)
2
5
ns
t₉₅
TDH and TDL Pairs Bit Cell Center to Center
99
100
101
ns
t₉₆
TDH and TDL Pairs Bit Cell Center to Boundary
49
50
51
ns
t₉₇
TDH and TDL Pairs Return to Zero from Last TDH
250
400
ns
t₉₈
Link Test Pulse Width
98
100
100
ns
t₉₉
Last TD Activity to Link Test Pulse
8
13
24
ms
t₁₀₀
Link Test Pulse to Data Separation
190
200
ns
281630 – 29
Figure 11-19 TPE Transmit Timings (Link Test Pulse)
281630 – 30
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