82595TX Datasheet, PDF (6/59 Pages) Intel Corporation – ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER

82595TX
1 3 1 BUS INTERFACE
ISA IEEE P996 PCMCIA 2 0
The 82595TX implements the full ISA bus interface
It is compatible with the IEEE spec P996 The
82595TX also interfaces to ISA bus implementations
that deviate from the IEEE spec by requiring early
assertion of the IOCHRDY signal and alternate host
address decode timing This alternate timing can be
configured in the 82595TX after a software test
which is run at initialization time The 82595TX can
also be configured for a PCMCIA bus interface de-
pending on the state of the PCMCIA ISA input pin
In this case the 82595TX implements the complete
PCMCIA interface compatible to the PCMCIA revi-
sion 2 0 specification
1 3 2 ETHERNET TWISTED PAIR ETHERNET
INTERFACE IEEE 802 3 SPECIFICATION
The 82595TX’s serial interface provides either an
AUI port interface or a Twisted Pair Ethernet (TPE)
interface The AUI port can be connected to an
Ethernet Transceiver cable drop providing a fully
compliant IEEE 802 3 AUI interface The TPE port
provides a fully compliant IEEE 10BASE-T interface
The 82595TX can automatically switch to whichever
port (TPE or AUI) is active
2 0 82595TX PIN DEFINITIONS
2 1 ISA Bus Interface
The ISA bus interface consists of three sections an Address Bus a Data Bus and a Control section
Symbol
Pin
No
Type
Name and Function
SA0
66
I
ADDRESS BUS These pins provide address decoding for up to 1 Kbyte of
SA1
67
SA2
68
address These pins also provide 4 Kbytes of IO addressing to support the
Plug N’ Play Standard
SA3
69
SA4
70
SA5
71
SA6
73
SA7
74
SA8
75
SA9
76
SA10
13
SA11
143
SA14
SA15
SA16
SA17
SA18
SA19
77
I
ADDRESS BUS These pins provide address decoding between the 16 Kbyte
78
and 1 Mbyte memory space This allows for decoding of a Boot EPROM or a
79
FLASH in 16K increments
80
81
82
6