82595TX Datasheet, PDF (7/59 Pages) Intel Corporation – ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER

82595TX
2 1 ISA Bus Interface (Continued)
Symbol
Pin
No
Type
Name and Function
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
46 I O DATA BUS This is the data interface between the 82595TX and the host
47
system This data is buffered by one (8-bit design) or two (16-bit design)
48
transceivers The 82595TX’s data lines should always be connected to
49
the B side of the data bus transceiver
52
53
54
55
56
57
58
59
62
63
64
65
AEN
20
I
ADDRESS ENABLE Active high signal indicates a DMA cycle is active
BALE
21
I
BUFFERED ADDRESS LATCH ENABLE Falling edge used to latch a
valid system address
SMEMR
14
I
MEMORY READ for system memory accesses below 1 Mbyte Active low
SMEMW
15
I
MEMORY WRITE for system memory accesses below 1 Mbyte Active
low
MEMR
16
8 16 Detect
I
MEMORY READ for system memory accesses above or below 1 Mbyte
Active low This pin also determines if the 82595TX is operating in an 8- or
16-bit system For 16-bit systems it should always be connected
MEMW
17
I
MEMORY WRITE for system memory accesses above or below 1 Mbyte
Active low
IOR
18
I
IO READ Active low
IOW
19
I
IO WRITE Active low
IOCS16
40
O IO CHIP SELECT 16 Active low open drain output which indicates that
an IO cycle access to the 82595TX solution is 16-bit wide Driven for IO
cycles to the local memory or to the 82595TX
IOCHRDY
37
O IO CHANNEL READY Active high open drain output When driven low it
extends host cycles to the 82595TX solution
SBHE
32
I
SYSTEM BUS HIGH ENABLE Active low input indicates a data transfer
on the high byte (D8 – D15) of the system bus (a 16-bit transfer)
INT0
INT1
INT2
INT3
INT4
26
O 82595TX INTERRUPT 0 – 4 One of these five pins is selected to be active
27
at a time (the other four are in Hi-Z state) by configuration These active
28
high outputs serve as interrupts to the host system
29
30
RESET DRV 12
I
RESET DRIVE Active high reset signal
7