82595TX Datasheet, PDF (24/59 Pages) Intel Corporation – ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER

82595TX
5 4 82595TX Status Interface
The Status of the 82595TX can be read from Regis-
ter 1 of Bank 0 with additional status information
contained in Register 0 (the Command Register)
Figure 5-3 shows these registers Other information
concerning the configuration and initialization of the
82595TX and its registers can be obtained by direct-
ly reading the 82595TX registers
When read the Command OP Code field indicates
which event (MC Done Init Done TDR Done or
DIAG Done) has been completed This field is valid
only when the EXEC INT Bit (Bank 0 Reg 1 Bit 3) is
set to a 1 Reading the Pointer field indicates which
bank the 82595TX is currently operating in Register
1 in Bank 0 contains the 82595TX interrupts status
as well as the current states of the RCV and Execu-
tion units of the 82595TX Resultant status from
events such as the completion of a transmission or
the reception of an incoming frame is contained in
the status field of the memory structures for these
particular events
6 0 INITIALIZATION
Upon either a software or hardware RESET the
82595TX enters into its initialization sequence
When the 82595TX is interfaced to an ISA bus the
82595TX reads information from its EEPROM and
Jumper block (if utilized) which configures critical pa-
rameters (IO Address mapping etc ) to allow initial
accesses to the 82595TX during the host system’s
initialization sequence and also access by the soft-
ware device driver The 82595TX can also be config-
ured (via the EEPROM) to automatically resolve any
conflicts to its IO address location either by moving
its IO address offset to an unused location in the
case that a conflict occurs or by using the Plug N’
Play Software to the I O address location This pro-
cess eliminates a large majority of LAN end-user
setup problems
The 82595TX can be configured to operate with ISA
systems that require early deassertion of the
IOCHRDY signal to its low (not ready) state The
82595TX along with its software driver can perform
a test at initialization to determine if early IOCHRDY
deassertion is required
The 82595TX when interfaced to a PCMCIA bus
simply powers up with default PCMCIA configuration
values enabled This is the only step for PCMCIA
initialization since the PCMCIA bus requires no se-
lection of Interrupts IO Space etc
7
6
5
4
3
2
1
0
Pointer
RCV
States
ABORT
EXECUTION EVENT
Reg 0 (CMD Reg)
EXEC
States
EXEC
TX
INT
INT
RX RX STP
INT
INT Reg 1 (Bank 0)
Figure 5-3 82595TX Status Information
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