82595TX Datasheet, PDF (11/59 Pages) Intel Corporation – ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER

82595TX
2 4 Miscellaneous Control
Symbol
Pin
No
Type
Name and Function
DIRL
42 O DIRECTION LOW Controls the direction of the low byte data bus
transceiver The direction defaults to always point in from the ISA bus to
the 82595TX (DIRL ^e 1) This direction is turned around (82595TX out to
ISA bus DIRL ^e 0) only in the case of a read access to the 82595TX
based solution
DIRH
45 O DIRECTION HIGH Controls the direction of the high byte data bus
transceiver The direction defaults to always point in from the ISA bus to
the 82595TX (DIRH ^e 1) This direction is turned around (82595TX out to
ISA bus DIRH ^e 0) only in the case of a read access to the 82595TX
based solution This signal is active for 16-bit accesses only
SMOUT
11 I O This active LOW signal when asserted places the 82595TX into a Power
Down mode The 82595TX will remain in power down mode until SMOUT
is unasserted If this line is unconnected to SMOUT from the system bus
it can be used as an active low output which when a POWER DOWN
command is issued to the 82595TX can be used to power down other
external components (this output function is enabled by configuration)
PCMCIA ISA 22
I
This pin when strapped low selects an ISA bus interface Strapped high
selects PCMCIA
J0
107
I
JUMPER input for selecting between 7 ISA IO spaces (also selects
J1
106 I O whether the IO location should be read from the EEPROM) These pins
J2
105 I O ^{should be connected to either V}CC ^{or GND The 82595TX reads the}
Jumper block during its initialization sequence
J0
GND
V_CC
GND
V_CC
GND
V_CC
GND
V_CC
J1
GND
GND
V_CC
V_CC
GND
GND
V_CC
V_CC
J2
GND
GND
GND
GND
V_CC
V_CC
V_CC
V_CC
IO Address
Address Contained in EEPROM
2A0h
280h
340h
300h
360h
350h
330h
2 5 JTAG Control
Symbol
Pin
No
Type
TDO
97 O
TMS
98
I
TCK
99
I
TDI
100
I
Name and Function
JTAG TEST DATA OUT
JTAG TEST MODE SELECT
JTAG TEST CLOCK
JTAG TEST DATA IN
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