82595TX Datasheet, PDF (27/59 Pages) Intel Corporation – ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER

82595TX
Status Field
The two bytes of the Status Field (Status 0 and
Status 1) are shown in detail in Figure 7-3 In a 16-bit
wide interface these two bytes will combine to form
one word This field is originally set to all 0’s by the
CPU as the XMT block is copied to memory It is
updated by the 82595TX upon completion of the
transmission
7 2 XMT Chaining
The 82595TX can transmit consecutive frames with-
out the CPU having issued a separate Transmit
command for each frame This is called Transmit
Chaining The 82595TX Transmit Chaining memory
structure for a 16-bit interface is shown in Figure 7-4
with an 8-bit interface shown in Figure 7-5 The
82595TX registers which control the memory struc-
ture are also shown The CPU places multiple XMT
blocks in the Transmit buffer The 82595TX will
transmit each frame in the chain reporting the
status for each frame in its status field If Concurrent
Processing is enabled the copy of additional frames
in a chain will take place while the first portion of the
chain (one or more frames) is being transmitted by
the 82595TX This chain can be dynamically updat-
ed by the CPU to add more frames to the chain The
transmit chain can be configured to terminate upon
an errored frame (maximum collisions underrun lost
CRS etc ) or it can continue to the next frame in the
chain The 82595TX can be configured to interrupt
upon completion of each transmission or to interrupt
at the end of the transmit chain only (it always inter-
rupts upon an errored condition)
7
6
5
TX DEF HRT BET MAX COL
COLL
X
TX OK
4
3
2
1
0
X
No OF COLLISIONS
Status 0
0
LTCOL LST CRS X UND RUN Status 1
Figure 7-3 Transmit Result
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