82595TX Datasheet, PDF (35/59 Pages) Intel Corporation – ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER

82595TX
10 0 APPLICATION NOTES
This section is intended to provide Ethernet LAN de-
signers with a basic understanding of how the
82595TX is used in a buffered LAN design
10 1 Bus Interface
The 82595TX Bus Interface unit integrates the inter-
face to both an ISA compatible bus and a PCMCIA
rev 2 0 bus Selection of the desired bus interface is
done by strapping the PCMCIA ISA pin accordingly
Two 74ALS245 transceivers are used to buffer the
82595TX’s data bus with the 82595TX providing the
control over the transceivers The data bus is not
buffered in a PCMCIA design The 82595TX also
provides the complete control and address interface
to the host system bus When the ISA bus interface
is selected it implements the complete ISA bus pro-
tocol When PCMCIA interface is selected the com-
plete PCMCIA bus interface protocol is implement-
ed
10 2 Local Memory Interface
The 82595TX’s local memory interface includes a
DMA unit which controls data transfers between the
82595TX and the local memory DRAM The
82595TX can support up to 64 Kbytes of local
DRAM
The 82595TX provides address decoding and con-
trol to allow access to an external Boot EPROM or a
FLASH Addition of a Boot EPROM or FLASH to an
ISA solution is optional The FLASH is always con-
tained as part of a PCMCIA solution The 82595TX
also supports a separate IA PROM if one is desired
For this example the IA is assumed to be stored in
the serial EEPROM for the ISA solution and in the
FLASH for the PCMCIA solution
10 3 EEPROM Interface (ISA Only)
The 82595TX provides a complete interface to a se-
rial EEPROM for ISA adapter designs For ISA moth-
erboard designs and PCMCIA designs the
EEPROM is not required The EEPROM is used to
store configuration information such as Memory and
IO Mapping Window Interrupt line selection Plug N’
Play resource data local bus width etc The
EEPROM is used to replace jumper blocks which
previously contained this type of information The
82595TX also contains an optional jumper interface
(J0–J2) These jumpers can be used to select the IO
mapping window of the solution In the case of this
design the jumper block is grounded (disabled) with
the IO mapping window being contained in the
EEPROM
10 4 Serial Interface
The 82595TX’s serial interface provides either an
AUI port interface or a Twisted Pair Ethernet (TPE)
interface The AUI port can be connected to an
Ethernet Transceiver cable drop to provide a fully
compliant IEEE 802 3 10BASE5 interface The AUI
port can also be interfaced to a transceiver device
on the adapter to provide a fully compliant IEEE
802 3 10BASE2 (Cheapernet) interface The TPE
port provides a fully compliant 10BASE-T interface
The 82595TX automatically enables either the AUI
or TPE interface depending on which medium is
connected to the chip This automatic selection can
be overridden by software configuration
10 4 1 AUI CIRCUIT
When used in conjunction with pulse transformers
the 82595TX provides a complete IEEE 802 3 AUI
interface In order to meet the 16V fault tolerance
specification of IEEE 802 3 a pulse transformer is
recommended The transformer should be placed
between the TRMT RCV and CLSN pairs of the
82595TX and the DO DI and CI pairs of the AUI
(DB-15) connector The pulse transformer should
have the following characteristics
 75 mH minimum inductance (100 mH recom-
mended)
 2000V isolation between the primary and second-
ary windings
 2000V isolation between the primaries of sepa-
rate transformers
 1 1 Turns ratio
The RCV and CLSN input pairs should each be ter-
minated by 78 7X g1% resistors
10 4 2 TPE CIRCUIT
The 82595TX provides the line drivers and receivers
needed to directly interface to the TPE analog filter
network The TPE receive section requires a 100X
termination resistor a filter section (filter isolation
transformer and a common mode choke) as de-
scribed by the 10BASE-T 802 3i-1990 specification
The TPE transmit section is implemented by con-
necting the 82595TX’s four TPE outputs (TDH TDH
TDL TDL) to a resistor summing network to form the
differential output signal The parallel resistance of
R5 and R6 sets the transmitters maximum output
voltage while the difference (R5^bR6) R5^aR6) is
used to reduce the amplitude of the second half of
the fat bit (100 ns) to a predetermined level This
predistortion reduces line overcharging a major
source of jitter in the TPE environment The output
of the summing network is then fed into the above
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