82595TX Datasheet, PDF (55/59 Pages) Intel Corporation – ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER

82595TX
Table 11-16 TPE Receive Timings
Symbol
Parameter
Min
Typ
Max
Unit
t₁₀₅
RD to RxD Bit Loss at Start of Packet
4
t₁₀₆
RD Invalid Bits Allowed at Start of Packet
t₁₀₇
RD to Internal Steady State Propagation Delay
t₁₀₈
RD to Internal Start Up Delay
t₁₀₉
RD Pair Bit Cell Center Jitter
t₁₁₀
RD Pair Bit Cell Boundry Jitter
t₁₁₁
RD Pair Held High from Last Valid
230
Position Transition
19
bits
1
bits
400
ns
24
ms
g13 5
ns
g13 5
ns
400
ns
Figure 11-20 TPE Receive Timings (End of Frame)
Symbol
t₁₂₀
t₁₂₁
t₁₂₂
Table 11-17 TPE Link Integrity Timings
Parameter
Min
Typ
Last RD Activity to Link Fault
(Link Loss Timer)
50
100
Minimum Received Linkbeat Separation⁽¹⁾
2
5
Maximum Received Linkbeat Separation⁽²⁾
25
50
NOTES
1 Linkbeats closer in time to this value are considered noise and rejected
2 Linkbeats further apart in time than this value are not considered consecutive and are rejected
281630 – 31
Max
Unit
150
ms
7
ms
150
ms
55