82595TX Datasheet, PDF (36/59 Pages) Intel Corporation – ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER

82595TX
mentioned filter and then to the 10BASE-T connec-
tor (RJ-45) Analog Front End solutions can be pur-
chased in a single-chip solution from several manu-
facturers The solution described in this data sheet
uses the Pulse Engineering (PE65434) AFE
10 5 2 CRYSTAL
The crystal should be adjacent to the 82595TX and
trace lengths should be as short as possible the X1
and X2 traces should be symmetrical
10 4 3 LED CIRCUIT
The 82595TX’s internal LED drivers support four
LED indicators displaying node status and activity
(i e Transmit data receive data collisions link in-
tegrity polarity correction and port (TPE AUI) To
implement the LED indicators connect the LED driv-
er output to an LED in series with a 510X resistor
tied to V_CC Each driver can sink up to 10 mA of
current with an output impedance of less than 50X
10 5 Layout Guidelines
10 5 1 GENERAL
The analog section as well as the entire board itself
should conform to good high-frequency practices
and standards to minimize switching transients and
parasitic interaction between various circuits To
achieve this follow these guidelines
Make power supply and ground traces as thick as
possible This will reduce high-frequency cross cou-
pling caused by the inductance of thin traces
Connect logic and chassis ground together
You must connect all V_CC pins to the same power
supply and all V_SS pins to the same ground plane
Use separate decoupling and noise conditions per
power-supply ground pin
Close signal paths to ground as close as possible to
their sources to avoid ground loops and noise cross
coupling
Use high-loss magnetic beads on power supply dis-
tribution lines
10 5 3 82595TX ANALOG DIFFERENTIAL
SIGNALS
The differential signals from the 82595TX to the
transformers analog front end and the connectors
should be symmetrical for each pair and as short as
possible
As a general rule the trace widths should be one to
three times the distance between the PCB layers to
eliminate excessive trace inductance
The differential signals should also be isolated from
the high speed logic signals on the same layer as
well as on any sublayers of the PCB
Group each of the circuits together but keep them
separate from each other Separate their grounds
In layout the circuitry from the connectors to the
filter network should have the ground and power
planes removed from beneath it This will prevent
ground noise from being induced into the analog
front end
All trace bends should not exceed 45 degrees
10 5 4 DECOUPLING CONSIDERATIONS
Four 0 1 mF ceramic capacitors should be used
Place one on each side in the center of the I C (V_CC
pins 23 51 89 125 are recommended) adjacent to
the 82595TX Connect the capacitors directly to the
V_CC pins on the 82595TX and then directly to the
ground plane In addition to the 0 1 mF capacitors a
10 mF tantalum should be used near one of the
82595TX’s V_CC pins The proximity of this capacitor
to the 82595TX is not as critical as in the case of the
0 1 mF capacitors Placement of this capacitor within
approximately one inch of the 82595TX is recom-
mended
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