82595TX Datasheet, PDF (47/59 Pages) Intel Corporation – ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER

82595TX
11 6 Local Memory Timings
11 6 1 DRAM TIMINGS
The 82595TX supports up to 80 ns DRAM produc-
ing
Word transfer every 400 ns
Byte transfer every 250 ns
Refresh cycle 200 ns
The 82595TX supports 64K x 4 or 256K x 4 DRAM in
fast page mode only Write cycles are produced in
EARLY WRITE mode This eliminates using the
DRAM OE signal (it must be connected to GND)
Symbol
T49
T50
T51
T52
T53
T54
T55
T56
T57
T58
T59
T60
T61
T62
T63
T64
T65
T66
T67
T68
T69
T70
T71
T72
T73
T74
T75
T76
T77
T78
Table 11-8 DRAM A C Characteristics
Parameter
Timing
Min
Max
Access Time from RAS
80
Access Time from CAS
30
Access Time from Column Address
40
CAS to Output Low Z
0
Output Buffer Turn-Off Delay Time
0
40
RAS Precharge Time
75
RAS Pulse Width
80
RAS Hold Time
30
CAS to RAS Precharge Time
20
RAS to CAS Delay Time
30
CAS Pulse Width
35
CAS Hold Time
80
Row Address Set-Up Time
0
Row Address Hold Time
15
Column Address Set-Up Time
0
Column Address Hold Time
20
Column Address Time Referenced to RAS
65
RAS to Column Address Delay Time
20
Column Address to RAS Lead Time
40
Write Command Set-Up Time
0
Write Command Hold Time
15
Write Command to CAS Lead Time
30
D_IN Set-Up Time
0
D_IN Hold Time
15
CAS Set-Up Time for
10
CAS before RAS Refresh
CAS Hold Time for CAS
25
before RAS Refresh
Fast Page Mode Cycle Time
55
Fast Page Mode CAS Precharge Time
15
Random Read or Write Cycle Time
190
RAS Precharge Time to CAS Active Time
100
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
47