82596CA Datasheet, PDF (8/76 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596CA
PIN DESCRIPTIONS (Continued)
Symbol
PQFP
Pin No
Type
Name and Function
ADS
124
O
ADDRESS STATUS The 82596 uses this tri-state pin to indicate to
indicate that a valid bus cycle has begun and that A31 – A2 BE3 – BE0
and W R are being driven It is asserted during t1 bus states This line
is floated after a Reset or when the bus is not acquired
RDY
130
I
READY Active low This signal is the acknowledgment from
addressed memory that the transfer cycle can be completed When
high it causes wait states to be inserted It is ignored at the end of the
first clock of the bus cycle’s data cycle This active-low signal does not
have an internal pull-up resistor This signal must meet the setup and
hold times to operate correctly
BRDY
2
I
BURST READY Active low Burst Ready like RDY indicates that the
external system has presented valid data on the data pins in response
to a Read or that the external system has accepted the 82596 data in
response to a Write request Also like RDY this signal is ignored at
the end of the first clock in a bus cycle If the 82596 can still receive
data from the previous cycle ADS will not be asserted in the next
clock cycle however Address and Byte Enable will change to reflect
the next data item expected by the 82596 BRDY will be sampled
during each succeeding clock and if active the data on the pins will be
strobed to the 82596 or to external memory (read write) BRDY
operates exactly like READY during the last data cycle of a burst
sequence and during nonburstable cycles
BLAST
128
O
BURST LAST A signal (active low) on this tri-state pin indicates that
the burst cycle is finished and when BRDY is next returned it will be
treated as a normal ready i e another set of addresses will be driven
with ADS or the bus will go idle BLAST is not asserted if the bus is not
acquired
AHOLD
117
I
ADDRESS HOLD This hold signal is active high it allows another bus
master to access the 82596 address bus In a system where an 82596
and an i486 processor share the local bus AHOLD allows the cache
controller to make a cache invalidation cycle while the 82596 holds the
address lines In response to a signal on this pin the 82596
immediately (i e during the next clock) stops driving the entire address
bus (A31– A2) the rest of the bus can remain active For example
data can be returned for a previously specified bus cycle during
Address Hold The 82596 will not begin another bus cycle while
AHOLD is active
BOFF
116
I
BACKOFF This signal is active low it informs the 82596 that another
bus master requires access to the bus before the 82596 bus cycle
completes The 82596 immediately (i e during the next clock) floats its
bus Any data returned to the 82596 while BOFF is asserted is ignored
BOFF has higher priority than RDY or BRDY if two such signals are
returned in the same clock period BOFF is given preference The
82596 remains in Hold until BOFF goes high then the 82596 resumes
its bus cycle by driving out the address and status and asserting ADS
LOCK
126
O
LOCK This tri-state pin is used to distinguish locked and unlocked bus
cycles LOCK generates a semaphore handshake to the CPU LOCK
can be active for several memory cycles it goes active during the first
locked memory cycle (t1) and goes inactive at the last locked cycle
(t2) This line is floated after a Reset or when the bus is not acquired
LOCK can be disabled via the sysbus byte in software
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