82596CA Datasheet, PDF (32/76 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596CA
OVRNERRS
This 32-bit quantity contains the number of frames known to be lost because the local system bus was not
available If the traffic problem lasts longer than the duration of one frame the frames that follow the first are
lost without an indicator and they are not counted This counter is updated if needed regardless of the RU
state
This 32-bit counter contains the number of collisions detected during frame reception This counter will only be
updated if at least 64 bytes of data are received before the collision occurs If a collision occurs before 64
bytes of data are received the frame is counted as a short frame If the collision occurs in the preamble no
counters are incremented
ACTION COMMANDS AND OPERATING MODES
This section lists all the Action Commands of the Command Unit Command Block List (CBL) Each command
contains the Command field the Status and Control fields the link to the next Action Command and any
command-specific parameters There are three basic types of action commands 82596 Configuration and
Setup Transmission and Diagnostics The following is a list of the actual commands
 NOP
 Transmit
 Individual Address Setup
 TDR
 Configure
 Dump
 MC Setup
 Diagnose
The 82596 has three addressing modes In the 82586 mode all the Action Commands look exactly like those
of the 82586
 82586 Mode The 82596 software and memory structure is compatible with the 82586
 32-Bit Segmented Mode The 82596 can access the entire system memory and use the two new memory
structures Simplified and Flexible while still using the segmented approach This does not require any
significant changes to existing software
 Linear Mode The 82596 operates in a flat linear 4 gigabyte memory space without segmentation It can
also use the two new memory structures
In the 32-bit Segmented mode there are some differences between the 82596 and 82586 action commands
mainly in programming and activating new 82596 features Those bits marked ‘‘don’t care’’ in the compatible
mode are not checked however we strongly recommend that those bits all be zeroes this will allow future
enchancements and extensions
In the Linear mode all of the address offsets become 32-bit address pointers All new 82596 features are
accessible in this mode and all bits previously marked ‘‘don’t care’’ must be zeroes
The Action Commands and all other 82596 memory structures must begin on even byte boundaries i e they
must be word aligned
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