82596CA Datasheet, PDF (76/76 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596CA
mm (inch)
290218 – 39
Figure 65 Detail M
REVISION SUMMARY
The following represents the key differences be-
tween version 004 and version 005 of the 82596CA
Data Sheet
1 Timings added for -16 MHz and -20 MHz specfi-
cations
The following represents the key differences be-
tween version 005 and version 006 of the 82596CA
Data Sheet
1 A description of the 82596CA C-stepping en-
hancements was added and the 82596CA B-step
information was removed
2 Description of BOFF pin changed BOFF may be
asserted in T1 in the 82596 C-step
3 Recommendation to use only one type of buffer
(either Simplified or Flexible) in any given linked
list
4 Added detailed description regarding operation
or RCVCDT counter
5 Added New Enhanced Big Endian Mode section
The New Enhanced Big Endian Mode applies
only to the 82596 C-stepping
6 Added programming recommendations regarding
RU and CU Start commands These warn against
Starting the CU while it is Active and Starting the
RU while it is Ready
7 Emphasized that the TDR command is a static
command and should not be used in an active
network
8 Improved 82596CA C-step timings were added
for all speeds
76