82596CA Datasheet, PDF (28/76 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596CA
Events can be cleared only by CPU acknowledgment If some events are not acknowledged by the ACK field
the Interrupt signal (INT) will be reissued after Channel Attention (CA) is processed Furthermore if a new
event occurs while an interrupt is set the interrupt is temporarily cleared to trigger edge-triggered interrupt
controllers
The CPU uses the Channel Attention line to cause the 82596 to examine the SCB This signal is trailing-edge
triggered the 82596 latches CA on the trailing edge The latch is cleared by the 82596 before the SCB
control command is read
31
ACK
ODD WORD
X CUC R RUC
RFA OFFSET
ALIGNMENT ERRORS
OVERRUN ERRORS
16 15
X X X X STAT
EVEN WORD
0 CUS 0 RUS
CBL OFFSET
CRC ERRORS
RESOURCE ERRORS
0
0 0 0 0 SCB
SCB a 4
SCB a 8
SCB a 12
Figure 18 SCB 82586 Mode
31
ODD WORD
16 15
ACK 0 CUC R RUC 0 0 0 0 STAT 0
RFA OFFSET
CRC ERRORS
ALIGNMENT ERRORS
RESOURCE ERRORS ( )
OVERRUN ERRORS ( )
RCVCDT ERRORS ( )
SHORT FRAME ERRORS
T-ON TIMER
In monitor mode these counters change function
EVEN WORD
CUS
RUS
CBL OFFSET
T-OFF TIMER
Figure 19 SCB 32-Bit Segmented Mode
0
T 0 0 0 SCB
SCB a 4
SCB a 8
SCB a 12
SCB a 16
SCB a 20
SCB a 24
SCB a 28
SCB a 32
31
ODD WORD
16 15
EVEN WORD
ACK 0 CUC R RUC 0 0 0 0 STAT 0 CUS
RUS
COMMAND BLOCK ADDRESS
RECEIVE FRAME AREA ADDRESS
CRC ERRORS
ALIGNMENT ERRORS
RESOURCE ERRORS ( )
OVERRUN ERRORS ( )
RCVCDT ERRORS ( )
SHORT FRAME ERRORS
T-ON TIMER
In MONITOR mode these counters change function
T-OFF TIMER
Figure 20 SCB Linear Mode
0
T 0 0 0 SCB
SCB a 4
SCB a 8
SCB a 12
SCB a 16
SCB a 20
SCB a 24
SCB a 28
SCB a 32
SCB a 36
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