82596CA Datasheet, PDF (25/76 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596CA
 82586 Mode
 A Linear address is a single 24-bit entity Address pins A₃₁ – A₂₄ are always zero
 A Segmented address uses a 24-bit base and a 16-bit offset
 32-bit Segmented Mode
 A Linear address is a single 32-bit entity
 A Segmented address uses a 32-bit base and a 16-bit offset
NOTE
In the previous two memory addressing modes each command header (CB TBD RFD RBD and SCB)
must wholly reside within one segment If the 82596 encounters a memory structure that does not follow this
restriction the 82596 will fetch the next contiguous location in memory (beyond the segment)
 Linear Mode
 A Linear address is a single 32-bit entity
 There are no Segmented addresses
Linear addresses are primarily used to address transmit and receive data buffers In the 82586 and 32-bit
Segmented modes segmented addresses (base plus offset) are used for all Command Blocks Buffer Descrip-
tors Frame Descriptors and System Control Blocks When using Segmented addresses only the offset
portion of the entity being addressed is specified in the block The base for all offsets is the same that of the
SCB See Table 1
LITTLE ENDIAN AND BIG ENDIAN BYTE ORDERING
The 82596 supports both Little Endian and Big Endian byte ordering for its memory structures
The 82596 A1 stepping supports Big Endian byte ordering for word and byte entities Dword entities are not
supported with 82596 A1 Big Endian byte ordering This results in slightly different 82596A1 memory struc-
tures for Big Endian operation These structures are defined in the 32-Bit LAN Components User’s Manual
The 82596 B stepping supports Big Endian byte ordering for Linear mode only All 82596 B 32-bit address
pointers are treated as 32-bit Big Endian entities however the SCB absolute address and statistical counters
are treated as two 16-bit Big Endian entities This 32-bit Big Endian entity support is configured through bit 7 in
the SYSBUS byte
The 82596 C-step has a New Enhanced Big Endian Mode where in Linear Addressing mode true 32-bit Big
Endian functionality is achieved New Enhanced Big Endian Mode is enabled exactly the same as the B-step
by setting bit 7 of the SYSBUS byte This mode is software compatible with the big endian mode of the B-step
with one exception no 32-bit addresses need to be swapped by software in the C-step In this new mode the
82596 C-step treats 32-bit address pointers as true 32-bit entities and the SCB absolute address and statistical
counters are still treated as two 16-bit big endian entities Not setting this mode will configure the 82596 C-step
to be 100% compatible to the A1-step big endian mode
NOTE
All 82596 memory entities must be word or dword aligned except the transmit buffers can be byte aligned
for the 82596 B or C-steppings
An example of a dword entity is a frame descriptor command status dword whereas the raw data of the frame
are byte entities Both 32- and 16-bit buses are supported When a 16-bit bus is used with Big Endian memory
organization data lines D₁₅ – D₀ are used The 82596 has an internal crossover that handles these swap
operations
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