82596CA Datasheet, PDF (36/76 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596CA
NOTE
The P bit is valid only in the new memory structure modes In 82586 mode this bit is disabled (i e no
prefetched mark)
7
MONITOR
X
X
0
FIFO LIMIT
BYTE 1
FIFO Limit (Bits 0–3)
MONITOR (Bits 6–7)
DEFAULT C8h
FIFO limit
Receive monitor options If the Byte Count of the configure
command is less than 12 bytes then these Monitor bits are ignored
7
0
SAV BF
1
0
0
0
0
RESUME RD
0
BYTE 2
SAV BF (Bit 7)
DEFAULT 40h
RESUME RD (Bit 1)
0 Received bad frames are not saved in the memory
1 Received bad frames are saved in the memory
0 The 82596 does not reread the next CB on the list when a CU Resume
Control Command is issued
1 The 82596 will reread the next CB on the list when a CU Resume
Control Command is issued This is available only on the 82596B step-
ping
7
LOOP BACK
MODE
PREAMBLE LENGTH
NO SRC
ADD INS
0
ADDRESS LENGTH
BYTE 3
ADR LEN (Bits 0–2)
NO SCR ADD INS (Bit 3)
PREAM LEN (Bits 4–5)
LP BCK MODE (Bits 6–7)
DEFAULT 26h
Address length (any kind)
No Source Address Insertion
In the 82586 this bit is called AL LOC
Preamble length
Loopback mode
7
BOF METD
EXPONENTIAL PRIORITY
0
0
LINEAR PRIORITY
BYTE 4
LIN PRIO (Bits 0–2)
EXP PRIO (Bits 4–6)
BOF METD (Bit 7)
DEFAULT 00h
Linear Priority
Exponential Priority
Exponential Backoff method
7
0
INTER FRAME SPACING
BYTE 5
INTERFRAME SPACING
DEFAULT 60h
Interframe spacing
36