82596CA Datasheet, PDF (63/76 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596CA
AC Characteristics (Continued)
82596CA C-STEP INPUT OUTPUT SYSTEM TIMINGS
C_L on all outputs is 50 pF unless otherwise specified
All timing requirements are given in nanoseconds
Symbol
Parameter
T22a
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
HLDA Hold Time
RESET Setup Time
RESET Hold Time
INT INT Valid Delay
CA and BREQ PORT Pulse Width
D0–D31 CPU PORT Access Setup Time
D0–D31 CPU PORT Access Hold Time
PORT Setup Time
PORT Hold Time
BOFF Setup Time
BOFF Hold Time
33 MHz
Min
Max
3
9
3
1
20
2T1
6
45
7
3
10
3
Notes
12
12
12
123
2
2
2
2
2
2
NOTES
Timings shown are for the 82596CA C-stepping For information regarding timings for the 82596CA A1 or B-step contact
your local Intel representative
1 RESET HLDA and CA are internally synchronized This timing is to guarantee recognition at next clock for RESET HLDA
and CA
2 All set-up hold and delay timings are at maximum frequency specification Fmax and must be derated according to the
following equation for operation at lower frequencies
Tderated e (Fmax Fopr) c T
where
Tderate e Specifies the value to derate the specification
Fmax e Maximum operating frequency
Fopr e Actual operating frequency
T e Specification at maximum frequency
This calculation only provides a rough estimate for derating the frequency For more detailed information contact your
Intel Sales Office for the data sheet supplement
3 CA pulse width need only be 1 T1 wide if the set up and hold times are met BREQ must meet setup and hold times and
need only be 1 T1 wide
TRANSMIT RECEIVE CLOCK PARAMETERS
Symbol
Parameter
T36
TxC Cycle
T38
TxC Rise Time
T39
TxC Fall Time
T40
TxC High Time
T41
TxC Low Time
T42
TxD Rise Time
T43
TxD Fall Time
T44
TxD Transition
T45
TxC Low to TxD Valid
T46
TxC Low to TxD Transition
T47
TxC High to TxD Transition
T48
TxC Low to TxD High (At End of Transition)
20 MHz
Min
Max
50
5
5
19
18
10
10
20
25
25
25
25
Notes
13
1
1
13
13
4
4
24
46
24
24
4
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