82596CA Datasheet, PDF (59/76 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596CA
AC Characteristics (Continued)
82596CA C-STEP INPUT OUTPUT SYSTEM TIMINGS
T_C ^e 0 C – ^a85 C V_CC ^e 5V g10% These timing assume the C_L on all outputs is 50 pF unless otherwise
specified C_L can be 20 pF to 120 pF however timings must be derated All timing requirements are given in
nanoseconds
Symbol
Parameter
20 MHz
Min
Max
Notes
Operating Frequency
12 5 MHz 20 MHz
1X CLK Input
T1
CLK Period
50
80
T1a
CLK Period Stability
0 1%
Adjacent CLK D
T2
CLK High
16
2 0V
T3
CLK Low
16
0 8V
T4
CLK Rise Time
6
0 8V to 2 0V
T5
CLK Fall Time
6
2 0V to 0 8V
T6
BEn LOCK and A2–A31 Valid Delay
3
20
T6a
BLAST PCHK Valid Delay
3
25
T7
BEn LOCK BLAST A2–A31 Float Delay
3
34
T8
W R and ADS Valid Delay
3
20
T9
W R and ADS Float Delay
3
34
T10
D0–D31 DPn Write Data Valid Delay
3
23
T11
D0–D31 DPn Write Data Float Delay
3
34
T12
HOLD Valid Delay
2
25
T13
CA and BREQ Setup Time
10
12
T14
CA and BREQ Hold Time
6
12
T15
BS16 Setup Time
12
2
T16
BS16 Hold Time
4
2
T17
BRDY RDY Setup Time
12
2
T18
BRDY RDY Hold Time
4
2
T19
D0–D31 DPn READ Setup Time
6
2
T20
D0–D31 DPn READ Hold Time
5
2
T21
AHOLD and HLDA Setup Time
15
12
T22
AHOLD Hold Time
4
12
T22a
HLDA Hold Time
5
12
T23
RESET Setup Time
12
12
T24
RESET Hold Time
4
12
T25
INT INT Valid Delay
1
23
T26
CA and BREQ PORT Pulse Width
2 T1
123
T27
D0–D31 CPU PORT Access Setup Time
6
2
T28
D0–D31 CPU PORT Access Hold Time
5
2
T29
PORT Setup Time
10
2
T30
PORT Hold Time
5
2
T31
BOFF Setup Time
12
2
T32
BOFF Hold Time
4
2
Timings shown are for the 82596CA C-Stepping For information regarding timings for the 82596CA A1 or B-Step contact
your local Intel representative
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