82596CA Datasheet, PDF (23/76 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596CA
INTERMEDIATE SYSTEM CONFIGURATION POINTER (ISCP)
The ISCP indicates the location of the System Control Block Often the SCP is in ROM and the ISCP is in RAM
The CPU loads the SCB address (or an equivalent data structure) into the ISCP and asserts CA This Channel
Attention signal causes the 82596 to begin its initialization procedure and to get the SCB address from the
ISCP and SCP In 82586 and 32-bit Segmented modes the SCP base address is also the base address of all
Command Blocks Frame Descriptors and Buffer Descriptors (but not buffers) All these data structures must
reside in one 64-KB segment however in Linear mode no such limitation is imposed
The following diagram illustrates the ISCP format
ODD WORD
EVEN WORD
31
16 15
87
A15
SCB OFFSET
A0
BUSY
A23
SCB BASE ADDRESS
u
XXXXXXXX
A31
A24
in 82586 mode
in 32-bit segmented mode
0
ISCP
A0 ISCP a 4
BUSY
SCB OFFSET
SCB BASE
Indicates that the 82596 is being initialized The CPU sets the ISCP to 01h before it gives
the first CA to the 82596 The ISCP is cleared by the 82596 after the SCB base and offset
are read Note that the most significant byte of the first word of the ISCP is not modified
when BUSY is cleared
This 16-bit quantity specifies the offset portion of the address of the SCB
Specifies the base portion of the address of the SCB The base of SCB is also the base of
all 82596 Command Blocks Frame Descriptors and Buffer Descriptors In the 82586
mode bits A31–A24 are considered to be zero
Figure 16 The Intermediate System Configuration Pointer 82586 and 32-Bit Segmented Modes
31
000
A31
ODD WORD
16 15
SCB ABSOLUTE ADDRESS
EVEN WORD
87
000
BUSY
0
ISCP
A0 ISCP a 4
BUSY
SCB ADDRESS
Indicates that the 82596 is being initialized The ISCP is set to 01h by the CPU before its
first CA to the 82596 It is cleared by the 82596 after the SCB address is read
This 32-bit quantity specifies the physical address of the SCB
Figure 17 The Intermediate System Configuration Pointer Linear Mode
INITIALIZATION PROCESS
The CPU sets up the SCP ISCP and the SCB structures and if desired an alternative SCP address It also
sets BUSY to 01h The 82596 is initialized when a Channel Attention signal follows a Reset signal causing the
82596 to access the System Configuration Pointer The sysbus byte the operational mode the bus throttle
timer triggering method the interrupt polarity and the state of LOCK are read After reset the Bus Throttle
timers are essentially disabled the T-ON value is infinite the T-OFF value is zero After the SCP is read the
82596 reads the ISCP and saves the SCB address In 82586 and 32-bit Segmented modes this address is
represented as a base address plus the offset (this base address is also the base address of all the control
blocks) In Linear mode the base address is also an absolute address The 82596 clears BUSY sets CX and
CNR to equal 1 in the SCB clears the SCB command word sends an interrupt to the CPU and awaits another
Channel Attention signal RESET configures the 82596 to its default state before CA is asserted
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