82596CA Datasheet, PDF (7/76 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596CA
PIN DESCRIPTIONS
Symbol
PQFP
Pin No
Type
CLK
9
I
D0 – D31
14 – 53
IO
DP0 – DP3
4–7
IO
PCHK
127
O
A31-A2
70 – 108
O
BE3 –BE0 109–114 O
WR
120
O
Name and Function
CLOCK The system clock input provides the fundamental timing for
the 82596 It is a 1X CLK input used to generate the 82596 clock and
requires TTL levels All external timing parameters are specified in
reference to the rising edge of CLK
DATA BUS The 32 Data Bus lines are bidirectional tri-state lines that
provide the general purpose data path between the 82596 and
memory With the 82596 the bus can be either 16 or 32 bits wide this
is determined by the BS16 signal The 82596 always drives all 32 data
lines during Write operations even with a 16-bit bus D31 – D0 are
floated after a Reset or when the bus is not acquired
These lines are inputs during a CPU Port access in this mode the CPU
writes the next address to the 82596 through the data lines During
PORT commands (Relocatable SCP Self-Test Reset and Dump) the
address must be aligned to a 16-byte boundary This frees the D₃ – D₀
lines so they can be used to distinguish the commands The following
is a summary of the decoding data
D0 D1 D2 D3 D31 – D4
Function
0000
0000 Reset
0 1 0 0 ADDR Relocatable SCP
1 0 0 0 ADDR Self-Test
1 1 0 0 ADDR Dump Command
DATA PARITY These are tri-stated data parity pins There is one
parity line for each byte of the data bus The 82596 drives them with
even-parity information during write operations having the same timing
as data writes Likewise even-parity information with the same timing
as read information must be driven back to the 82596 over these pins
to ensure that the correct parity check status is indicated by the
82596
PARITY CHECK This pin is driven high one clock after RDY to inform
Read operations of the parity status of data sampled at the end of the
previous clock cycle When driven low it indicates that incorrect parity
data has been sampled It only checks the parity status of enabled
bytes which are indicated by the Byte Enable and Bus Size signals
PCHK is only valid for one clock time after data read is returned to the
82596 i e it is inactive (high) at all other times
ADDRESS LINES These 30 tri-stated Address lines output the
address bits required for memory operation These lines are floated
after a Reset or when the bus is not acquired
BYTE ENABLE These tri-stated signals are used to indicate which
bytes are involved with the current memory access The number of
Byte Enable signals asserted indicates the physical size of the data
being transferred (1 2 3 or 4 bytes)
 BE0 indicates D7–D0
 BE1 indicates D15–D8
 BE2 indicates D23–D16
 BE3 indicates D31–D24
These lines are floated after a Reset or when the bus is not acquired
WRITE READ This dual function pin is used to distinguish Write and
Read cycles This line is floated after a Reset or when the bus is not
acquired
7