82596CA Datasheet, PDF (56/76 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596CA
where
EOF
F
ACT COUNT
NEXT BD ADDRESS
BUFFER ADDRESS
EL
P
SIZE
Indicates that this is the last buffer related to the frame It is cleared by the CPU
before starting the RU and is written by the 82596 at the end of reception of the
frame
Indicates that this buffer has already been used The Actual Count has no meaning
unless the F bit equals one This bit is cleared by the CPU before starting the RU
and is set by the 82596 after the associated buffer has been This bit has the same
meaning as the Complete bit in the RFD and CB
This 14-bit quantity indicates the number of meaningful bytes in the buffer It is
cleared by the CPU before starting the RU and is written by the 82596 after the
associated buffer has already been used In general after the buffer is full the
Actual Count value equals the size field of the same buffer For the last buffer of
the frame Actual Count can be less than the buffer size
The offset (absolute address in the Linear mode) of the next RBD on the list It is
meaningless if EL^e1
The starting address of the memory area that contains the received data In the
82586 mode this is a 24-bit address (with pins A24 – A31^e0) In the 32-bit Seg-
mented and Linear modes this is a 32-bit address
Indicates that the buffer associated with this RBD is last in the FBL
This bit indicates that the 82596 has already prefetched the RBDs and any change
in the RBD data will be ignored This bit is valid only in the new 82596 memory
modes and if this feature has been enabled during configure command The
82596 Prefetches the RBDs in locked cycles after prefetching the RBD the 82596
performs a write cycle where the P bit is set to one and the rest of the data remains
unchanged The CPU is responsible for resetting it in all RBDs The 82596 will not
check this bit before setting it
This 14-bit quantity indicates the size in bytes of the associated buffer This quan-
tity must be an even number
56