EP82562ET Datasheet, PDF (7/40 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

Networking Silicon — 82562ET
2.0
82562ET Architectural Overview
The 82562ET is a highly integrated Platform LAN Connect device that combines a 10BASE-T and
100BASE-TX physical layer interfaces. The 82562ET supports a single interface fully compliant
with the IEEE 802.3 standard. Figure 1 provides a block diagram of the 82562ET architecture.
Figure 1. 82562ET Block Diagram
RDN/RDP
TDN/ TDP
Digital
Equalizer
Adaptation
Equalizer &
BLW correction
Digital Clock
Recovery (100)
CRS/Link 10
Detection
Digital Clock
Recovery (10)
Transmit DAC
10/100
Bias & Band-
Gap Voltage
Circuit
Clock
Generator
100Base-TX
PCS
10Base-T
PCS
Auto-
Negotiation
Control
Registers
Port LED
Drivers
LILED
ACTLED
SPEEDLED
LAN
Connect
Interface
LAN_RSTSYNC
LAN_TXD[2:0]
3
3
LAN_RXD[2:0]
LAN_CLK
X1
Crystal
X2
25 MHz
The 8252ET is a 3.3 V device in a 48-pin Shrink Small Outline Package (SSOP). This document
describes the architecture of the device in all modes of operation.
Four pins, test Enable (TESTEN), Test Clock (ISOL_TCK), Test Input (ISOL_TI), and Test
Execute (ISOL_EX), define the general operation of the device. Table 1 shows the pin settings for
the different modes of operation.
Table 1. 82562ET Hardware Configuration
Mode of Operation TESTEN ISOL_TCK ISOL_TI ISOL_EX
Comments
Normal operating
0
0
0
0
The ISOL_TCK, ISOL_TI,
mode
and ISOL_EX pins can
remain floating.
Isolate mode
(Tri-state and full
0
1
1
1
The device is in tri-state
and power-down mode.
power-down mode)
The device is in tri-state
1
1
1
1
and the fully powered
down.
XOR Tree
The XOR Tree is used for
1
0
0
0
board testing and tri-state
mode.
NOTE: Combinations not shown in Table 1 are reserved and should not be used.
Datasheet
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