EP82562ET Datasheet, PDF (25/40 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

Networking Silicon — 82562ET
5.2
5.3
5.3.1
Bit(s)
Name
Description
2
Next Page Able 0 = 0 = Local drive is not Next Page able
1 = Local drive is Next Page able
1
Page Received This bit clears itself on read.
0 = New Page not received
1 = New Page received
0
Link Partner Auto- 0 = Link Partner is not Auto-Negotiation able
Negotiation Able _{1 = Link Partner is Auto-Negotiation able}
Default
0
R/W
RO
0
RO
SC
LH
0
RO
Medium Dependent Interface Registers 8 through 15
Registers eight through fifteen are reserved for IEEE.
Medium Dependent Interface Registers 16 through 31
Register 16: PHY Status and Control Register Bit Definitions
Bit(s)
Name
Description
15:14
13
12
11
10
9
8
7
Reserved
These bits are reserved and should be set to 00b.
Reduced Power
Down Disable
This bit disables the automatic reduced power down.
0 = Enable automatic reduced power down
1 = Disable automatic reduced power down
Reserved
This bit is reserved and should be set to 0b.
Receive De-
This bit indicates status of the 100BASE-TX Receive
Serializer In-Sync De-Serializer In-Sync.
Indication
100BASE-TX
Power-Down
This bit indicates the power state of 100BASE-TX
PHY unit.
0 = Normal operation
1 = Power-down
10BASE-T
Power-Down
This bit indicates the power state of 10BASE-T PHY
unit.
0 = Normal operation
1 = Power-Down
Polarity
This bit indicates 10BASE-T polarity.
0 = Normal polarity
1 = Reverse polarity
Reserved
This bit is reserved and should be set to 0b.
Default
00
1
R/W
RW
RW
0
RW
--
RO
1
RO
1
RO
--
RO
0
RO
Datasheet
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